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公开(公告)号：US20200020847A1
公开(公告)日：2020-01-16
申请号：US16286718
申请日：2019-02-27
发明人： Kilho LEE , Gwanhyeob KOH , Yongjae KIM , Yoonjong SONG
摘要： A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.
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公开(公告)号：US20180358056A1
公开(公告)日：2018-12-13
申请号：US15854551
申请日：2017-12-26
发明人： Kilho LEE , Gwanhyeob KOH , Junhee LIM , Hongsoo KIM , Chang-hoon JEON
IPC分类号： G11C5/06 , G11C16/04 , G11C11/16 , H01L25/18 , H01L27/1157 , H01L27/22 , H01L27/11573 , H01L43/10
CPC分类号： G11C5/06 , G11C11/005 , G11C11/161 , G11C13/0002 , G11C13/0004 , G11C16/0483 , G11C2213/72 , G11C2213/76 , H01L25/18 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/222 , H01L43/10
摘要： A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
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公开(公告)号：US20210134884A1
公开(公告)日：2021-05-06
申请号：US17088168
申请日：2020-11-03
发明人： Kilho LEE , Gwanhyeob KOH , Ilmok PARK , Junhee LIM
IPC分类号： H01L27/24 , H01L27/1157 , G11C11/16 , H01L27/11582 , H01L27/11573 , H01L27/22 , H01L27/11575 , G11C14/00 , G11C5/02 , G11C16/04
摘要： Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.
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公开(公告)号：US20190267046A1
公开(公告)日：2019-08-29
申请号：US16411106
申请日：2019-05-13
发明人： Kilho LEE , Gwanhyeob KOH , Junhee LIM , Hongsoo KIM , Chang-hoon JEON
IPC分类号： G11C5/06 , H01L27/11573 , H01L27/22 , H01L27/1157 , H01L43/10 , G11C13/00 , H01L25/18 , G11C11/16 , G11C16/04
摘要： A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
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公开(公告)号：US20190259437A1
公开(公告)日：2019-08-22
申请号：US16285295
申请日：2019-02-26
发明人： Boyoung SEO , Seongui SEO , Gwanhyeob KOH , Yongkyu LEE
摘要： A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.
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6.发明公开公开(公告)号：US20240313782A1
公开(公告)日：2024-09-19
申请号：US18410351
申请日：2024-01-11
发明人： Sang-Koog KIM , Junhoe KIM , Gyuyoung PARK , Gwanhyeob KOH , Kilho LEE
摘要： An operating method of a chaotic computer including a chaotic logic device includes setting a first initial value based on a first initial state corresponding to a first logical operation, applying the set first initial value to the chaotic logic device, setting a first input value to be applied to the chaotic logic device based on first input data, applying the first input value to the chaotic logic device, generating a chaos signal to have the chaotic logic device operate in a chaotic mode, applying the chaos signal to the chaotic logic device, and measuring a first output value from the chaotic logic device operating based on the first input value and the chaos signal, and generating first output data based on the first output value. The chaotic logic device includes a magnetic thin film configured to have spin soliton formed therein.
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公开(公告)号：US20210257404A1
公开(公告)日：2021-08-19
申请号：US17028034
申请日：2020-09-22
发明人： Kilho LEE , Gwanhyeob KOH , Woojin KIM
IPC分类号： H01L27/22 , H01L23/522 , H01L43/12 , H01L21/768
摘要： An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height.
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公开(公告)号：US20210104575A1
公开(公告)日：2021-04-08
申请号：US16848010
申请日：2020-04-14
发明人： Kilho LEE , Gwanhyeob KOH
摘要： A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.
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公开(公告)号：US20180309052A1
公开(公告)日：2018-10-25
申请号：US16018700
申请日：2018-06-26
发明人： Shinhee HAN , Kiseok SUH , KyungTae NAM , Woojin KIM , Kwangil SHIN , Minkyoung JOO , Gwanhyeob KOH
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.
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