公开(公告)号：US11791286B2

公开(公告)日：2023-10-17

申请号：US17405487

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-ji Min ,  Seok-hyun Lee

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05556 ,  H01L2924/00012 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014

Abstract: Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance.

公开(公告)号：US20200219834A1

公开(公告)日：2020-07-09

申请号：US16819851

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-youn KIM ,  Seok-hyun Lee ,  Youn-ji Min ,  Kyoung-lim Suk ,  Seok-won Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498

Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.

公开(公告)号：US11101231B2

公开(公告)日：2021-08-24

申请号：US16819851

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-youn Kim ,  Seok-hyun Lee ,  Youn-ji Min ,  Kyoung-lim Suk ,  Seok-won Lee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L23/498

Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.