公开(公告)号：US20230095154A1

公开(公告)日：2023-03-30

申请号：US18075747

申请日：2022-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwook Park ,  Yongbum Jeung ,  Seeyoun Kwon ,  Sangwoo Yu ,  Seunga Lee ,  Jeock Lee

IPC: H04R1/10 ,  H04R1/28 ,  H04R1/08

Abstract: An electronic device wearable on a body may include: a first case configured to at least partially contact the body when the electronic device is worn on the body; a second case coupled to the first case, the second case being configured to, at an exposed area on an outer surface of the second case, be exposed when the electronic device is worn on the body; a first acoustic hole configured to penetrate the second case in the exposed area; a second acoustic hole configured to penetrate the second case at a position different from the first acoustic hole; and an acoustic dimple recessed into the outer surface of the second case and extending from the second acoustic hole.

公开(公告)号：US09583440B2

公开(公告)日：2017-02-28

申请号：US14792979

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekjung Kim ,  Myung-Ho Kong ,  Heesook Park ,  Youngwook Park ,  Mansug Kang ,  Seonghwee Cheong

IPC: H01L23/48 ,  H01L23/532 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L23/528 ,  H01L27/22 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L23/53266 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/228 ,  H01L28/91 ,  H01L29/0642 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.

Abstract translation: 半导体存储器件可以包括在场隔离区域上交叉并穿过器件的有源区的第一导线，其中第一导线可以包括被掺杂的第一导电图案，第二导电图案和金属硅 在第一和第二导电图案之间的氮化物图案，并且可以被配置为在金属 - 氮化硅图案的下边界处提供与第一导电图案的接触，并且被配置为在金属 - 氮化硅图案的上边界处提供扩散阻挡层， 具有第二导电图案的氮化硅图案。

公开(公告)号：US20250040132A1

公开(公告)日：2025-01-30

申请号：US18626728

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeseop Choi ,  Byunghoon Kim ,  Junho Kim ,  Youngwook Park ,  Jiho Park ,  Jungwoo Lee ,  Jihyun Hwang ,  Minho Choi

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, where the substrate includes at least one first active pattern in the cell region and a second active pattern in the core region; a first trench defined by the at least one first active pattern; and a second trench defined by the second active pattern, where an inner sidewall of the first trench defines first recesses that extend into the at least one first active pattern, an inner sidewall of the second trench defines second recesses that extend into the second active pattern, a distance between two adjacent first recesses from among the first recesses in the vertical direction corresponds to a first height, a distance between two adjacent second recesses from among the second recesses in the vertical direction corresponds to a second height.

公开(公告)号：US20230085456A1

公开(公告)日：2023-03-16

申请号：US17859472

申请日：2022-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk Chae ,  Dongsik Kong ,  Youngwook Park ,  Jihoon Kim ,  Myung-Hyun Baek ,  Ju Hyung We ,  Jun-Bum Lee

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.