公开(公告)号：US20230085456A1

公开(公告)日：2023-03-16

申请号：US17859472

申请日：2022-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk Chae ,  Dongsik Kong ,  Youngwook Park ,  Jihoon Kim ,  Myung-Hyun Baek ,  Ju Hyung We ,  Jun-Bum Lee

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.

公开(公告)号：US09673276B2

公开(公告)日：2017-06-06

申请号：US15194066

申请日：2016-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junsoo Kim ,  Dongjin Lee ,  Dongsoo Woo ,  Jun-Bum Lee ,  Sang-Il Han

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L29/0653 ,  H01L27/088 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.