公开(公告)号：US11651995B2

公开(公告)日：2023-05-16

申请号：US17026525

申请日：2020-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkuk Kim ,  Yunseung Kang ,  Oik Kwon ,  Jungik Oh ,  Sujin Jeon

IPC: H01L23/532 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/2481 ,  H01L43/12 ,  H01L45/1675 ,  H01L45/1683 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L43/02 ,  H01L45/06 ,  H01L45/141

Abstract: A memory device including a plurality of first conductive lines arranged on a substrate and spaced apart from each other in a first direction parallel to a top surface of the substrate; a plurality of capping liners on sidewalls of each of the plurality of first conductive lines, the plurality of capping liners having top surfaces at a vertical level equal to top surfaces of the plurality of first conductive lines, and bottom surfaces at a vertical level higher than bottom surfaces of the plurality of first conductive lines; and an insulating layer on the substrate, the insulating layer filling spaces between the plurality of first conductive lines and covering sidewalls of the plurality of capping liners.

公开(公告)号：US11723221B2

公开(公告)日：2023-08-08

申请号：US17113609

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kuk Kim ,  Yunseung Kang ,  Oik Kwon ,  Yeonji Kim ,  Sujin Jeon

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  H10N70/063

Abstract: A three-dimensional (3D) semiconductor memory device including first cell stacks arranged in first and second directions; second cell stacks disposed on the first cell stacks and arranged in the first and second directions; first conductive lines extending in the first direction and provided between a substrate and the first cell stacks; common conductive lines extending in the second direction and provided between the first and second cell stacks; etch stop patterns extending in the second direction and provided between the common conductive lines and top surfaces of the first cell stacks; second conductive lines extending in the first direction and provided on the second cell stacks; and a capping pattern covering a sidewall of the common conductive lines and a sidewall of the etch stop patterns, wherein each of the common conductive lines has a second thickness greater than a first thickness of each of the first conductive lines.

公开(公告)号：US20190214273A1

公开(公告)日：2019-07-11

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.

公开(公告)号：US10522366B2

公开(公告)日：2019-12-31

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.