公开(公告)号：US20230084694A1

公开(公告)日：2023-03-16

申请号：US17735306

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANMI LEE ,  Sangwuk Park ,  Yejeong Seo ,  Sanggyo Chung

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/528

Abstract: A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.

公开(公告)号：US12293921B2

公开(公告)日：2025-05-06

申请号：US18497172

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/3065 ,  H10B12/00

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US20210217625A1

公开(公告)日：2021-07-15

申请号：US17022208

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/455 ,  C23C16/56 ,  C23C16/40 ,  H01L21/3065 ,  H01L27/108

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US11842899B2

公开(公告)日：2023-12-12

申请号：US17022208

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/455 ,  C23C16/56 ,  C23C16/40 ,  H01L21/3065 ,  H10B12/00

CPC classification number: H01L21/3088 ,  C23C16/401 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US10910231B2

公开(公告)日：2021-02-02

申请号：US16453481

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Kyoung Ha Eom ,  Hyunchul Lee ,  Sounghee Lee ,  Jiseung Lee

IPC: H01L21/311 ,  H01L21/308

Abstract: A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.

公开(公告)号：US20230377889A1

公开(公告)日：2023-11-23

申请号：US18125873

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggyo Chung ,  Chanmi Lee ,  Seunghee Han ,  Jungpyo Hong

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144

Abstract: Provided is a method for manufacturing a semiconductor device, in which a mask layer, a buffer layer, and a first mandrel layer are sequentially stacked on a substrate including a first region and a second region. First mandrel patterns are formed on the buffer layer in the first region, and a second mandrel pattern covering the buffer layer in the second region is formed. A first spacer contacting side walls of the first mandrel pattern and the second mandrel pattern is formed on the buffer layer. The first mandrel patterns are removed. A buffer layer pattern and a preliminary mask pattern are formed on the substrate. The second mandrel pattern is removed. In addition, a mask pattern is formed. The buffer layer includes a material having lower electrical conductivity than the mask layer and having etching selectivity with respect to the mask layer.

公开(公告)号：US20190214273A1

公开(公告)日：2019-07-11

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.

公开(公告)号：US20240063024A1

公开(公告)日：2024-02-22

申请号：US18497172

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/455 ,  C23C16/56 ,  C23C16/40 ,  H01L21/3065 ,  H10B12/00

CPC classification number: H01L21/3088 ,  C23C16/45525 ,  C23C16/56 ,  C23C16/401 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3085 ,  H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US10522366B2

公开(公告)日：2019-12-31

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.