公开(公告)号：US09859363B2

公开(公告)日：2018-01-02

申请号：US15155639

申请日：2016-05-16

Applicant: SANDISK TECHNOLOGIES, LLC.

Inventor： Zhenyu Lu ,  Kota Funayama ,  Chun-Ming Wang ,  Jixin Yu ,  Chenche Huang ,  Tong Zhang ,  Daxin Mao ,  Johann Alsmeier ,  Makoto Yoshida ,  Lauren Matsumoto

IPC: H01L29/06 ,  H01L21/76 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/24 ,  H01L27/112

CPC classification number: H01L29/0649 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.

公开(公告)号：US20190259698A1

公开(公告)日：2019-08-22

申请号：US15898544

申请日：2018-02-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuji Takahashi ,  Chenche Huang ,  Chun-Ming Wang ,  Vincent Shih

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A device structure includes an array of semiconductor devices located in an array region over a substrate, metal lines laterally extending from the device region to a peripheral interconnection region, and interconnect via structures located in the peripheral interconnection region, and contacting a portion of a respective one of the plurality of metal lines. The metal lines include a first metal line and a second metal line each having a serpentine region which contacts a respective interconnect via structure.

公开(公告)号：US10553537B2

公开(公告)日：2020-02-04

申请号：US15898544

申请日：2018-02-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuji Takahashi ,  Chenche Huang ,  Chun-Ming Wang ,  Vincent Shih

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24

Abstract: A device structure includes an array of semiconductor devices located in an array region over a substrate, metal lines laterally extending from the device region to a peripheral interconnection region, and interconnect via structures located in the peripheral interconnection region, and contacting a portion of a respective one of the plurality of metal lines. The metal lines include a first metal line and a second metal line each having a serpentine region which contacts a respective interconnect via structure.