公开(公告)号：US20190280002A1

公开(公告)日：2019-09-12

申请号：US16020739

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.

公开(公告)号：US10388666B1

公开(公告)日：2019-08-20

申请号：US16020739

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11573

Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.

公开(公告)号：US10020363B2

公开(公告)日：2018-07-10

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US09780034B1

公开(公告)日：2017-10-03

申请号：US15183195

申请日：2016-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Kota Funayama ,  Ryoichi Ehara ,  Youko Furihata ,  Zhenyu Lu ,  Tong Zhang ,  Tadashi Nakamura

IPC: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.

公开(公告)号：US20180122905A1

公开(公告)日：2018-05-03

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US20190280003A1

公开(公告)日：2019-09-12

申请号：US16020817

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kensuke Yamaguchi ,  James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: Multiple tier structures are stacked over a substrate. Each tier structure includes an alternating stack of insulating layers and sacrificial material layers and a retro-stepped dielectric material portion overlying the alternating stack. Multiple types of openings are formed concurrently during formation of each tier structure. Openings concurrently formed through each tier structure can include at least two types of openings that may be selected from through-tier memory openings, through-tier support openings, and through-tier staircase-region openings. Each through-tier opening is filled with a respective through-tier sacrificial opening fill structure. Stacks of through-tier sacrificial opening fill structures can be removed in stages to form various device components, which include memory stack structures, support pillar structures, and staircase-region contact via structures. The sacrificial material layers are replaced with electrically conductive layers, which are laterally electrically isolated from the staircase-region contact via structures by annular insulating spacers.

公开(公告)号：US10355009B1

公开(公告)日：2019-07-16

申请号：US16020637

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/822

Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.

公开(公告)号：US09985098B2

公开(公告)日：2018-05-29

申请号：US15458200

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

公开(公告)号：US10297610B2

公开(公告)日：2019-05-21

申请号：US15818061

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Shinsuke Yada ,  Akihisa Sai ,  Sayako Nagamine ,  Takashi Orimoto ,  Tong Zhang

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US20180261671A1

公开(公告)日：2018-09-13

申请号：US15976442

申请日：2018-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.