公开(公告)号：US20180182771A1

公开(公告)日：2018-06-28

申请号：US15445579

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiying Costa ,  Daxin Mao ,  Christopher Petti ,  Dana Lee ,  Yao-Sheng Lee

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.

公开(公告)号：US10008570B2

公开(公告)日：2018-06-26

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Kento Kitamura ,  Tong Zhang ,  Chun Ge ,  Yanli Zhang ,  Satoshi Shimizu ,  Yasuo Kasagi ,  Hiroyuki Ogawa ,  Daxin Mao ,  Kensuke Yamaguchi ,  Johann Alsmeier ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

公开(公告)号：US10354956B1

公开(公告)日：2019-07-16

申请号：US15863205

申请日：2018-01-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Daxin Mao ,  Hiroyuki Ogawa ,  Johann Alsmeier

IPC: H01L27/28 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/528 ,  H01L21/3105 ,  H01L23/532 ,  H01L29/04 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.

公开(公告)号：US10217746B1

公开(公告)日：2019-02-26

申请号：US15867881

申请日：2018-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tae-Kyung Kim ,  Raghuveer S. Makala ,  Yanli Zhang ,  Hiroyuki Kinoshita ,  Daxin Mao ,  Jixin Yu ,  Yiyang Gong ,  Kazuto Watanabe ,  Michiaki Sano ,  Haruki Urata ,  Akira Takahashi

IPC: H01L27/105 ,  H01L21/768 ,  H01L27/24 ,  H01L23/535 ,  H01L45/00

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electrically conductive layers.

公开(公告)号：US10269620B2

公开(公告)日：2019-04-23

申请号：US15274451

申请日：2016-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Zhenyu Lu ,  Hiroyuki Ogawa ,  Daxin Mao ,  Kensuke Yamaguchi ,  Sung Tae Lee ,  Yao-sheng Lee ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11548

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

公开(公告)号：US10256248B2

公开(公告)日：2019-04-09

申请号：US15175450

申请日：2016-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu Lu ,  Jixin Yu ,  Johann Alsmeier ,  Fumiaki Toyama ,  Yuki Mizutani ,  Hiroyuki Ogawa ,  Chun Ge ,  Daxin Mao ,  Yanli Zhang ,  Alexander Chu ,  Yan Li

IPC: H01L27/11582 ,  H01L21/48 ,  H01L23/498 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.

公开(公告)号：US20190214344A1

公开(公告)日：2019-07-11

申请号：US15863205

申请日：2018-01-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Daxin Mao ,  Hiroyuki Ogawa ,  Johann Alsmeier

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/04 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/3105

CPC classification number: H01L23/535 ,  H01L21/31053 ,  H01L21/76846 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04

Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.

公开(公告)号：US09859363B2

公开(公告)日：2018-01-02

申请号：US15155639

申请日：2016-05-16

Applicant: SANDISK TECHNOLOGIES, LLC.

Inventor： Zhenyu Lu ,  Kota Funayama ,  Chun-Ming Wang ,  Jixin Yu ,  Chenche Huang ,  Tong Zhang ,  Daxin Mao ,  Johann Alsmeier ,  Makoto Yoshida ,  Lauren Matsumoto

IPC: H01L29/06 ,  H01L21/76 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/24 ,  H01L27/112

CPC classification number: H01L29/0649 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.

公开(公告)号：US10249640B2

公开(公告)日：2019-04-02

申请号：US15176674

申请日：2016-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Zhenyu Lu ,  Alexander Chu ,  Kensuke Yamaguchi ,  Hiroyuki Ogawa ,  Daxin Mao ,  Yan LI ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

公开(公告)号：US10056399B2

公开(公告)日：2018-08-21

申请号：US15445579

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiying Costa ,  Daxin Mao ,  Christopher Petti ,  Dana Lee ,  Yao-Sheng Lee

IPC: H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.