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    Three-dimensional memory device containing deformation resistant trench fill structure and methods of making the same
    1.
    发明授权
    Three-dimensional memory device containing deformation resistant trench fill structure and methods of making the same 有权

    公开(公告)号：US12288755B2

    公开(公告)日：2025-04-29

    申请号：US17807266

    申请日：2022-06-16

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Koichi Matsuno

    IPC: H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner having the first Young's modulus, a vertically alternating sequence of insulating plates and dielectric material plates at least partially laterally surrounded by the dielectric moat fill structure, and an interconnection via structure vertically extending the vertically alternating sequence.

    Semiconductor device manufacturing process including forming a bonded assembly and substrate recycling
    2.
    发明授权
    Semiconductor device manufacturing process including forming a bonded assembly and substrate recycling 有权

    公开(公告)号：US12288719B2

    公开(公告)日：2025-04-29

    申请号：US17659057

    申请日：2022-04-13

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Takuya Maehara

    IPC: H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A method includes forming an etch stop material layer and a planar sacrificial spacer layer over a front surface of a first substrate, forming an insulating encapsulation layer over the planar sacrificial spacer layer and on a backside surface and a side surface of the first substrate, forming a continuous structure including first semiconductor devices over a top surface of the insulating encapsulation layer, etching inter-die trenches within the continuous structure to divide the continuous structure, bonding the divided continuous structure to second semiconductor devices located over a second substrate, selectively removing the planar sacrificial spacer layer by performing a wet etch process in which an isotropic etchant is introduced into the inter-die trenches, and detaching the first substrate from an assembly of the second substrate, the second semiconductor devices, and the divided continuous structure after the removing the planar sacrificial spacer layer.

    Three-dimensional memory device with staircase etch stop structures and methods for forming the same
    4.
    发明授权
    Three-dimensional memory device with staircase etch stop structures and methods for forming the same 有权

    公开(公告)号：US12279425B2

    公开(公告)日：2025-04-15

    申请号：US17411726

    申请日：2021-08-25

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Kenichi Shimomura

    IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

    Three-dimensional memory device including vertical stack of tubular graded silicon oxynitride portions
    6.
    发明授权
    Three-dimensional memory device including vertical stack of tubular graded silicon oxynitride portions 有权

    公开(公告)号：US12255242B2

    公开(公告)日：2025-03-18

    申请号：US17587470

    申请日：2022-01-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Koichi Matsuno

    IPC: H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H10B43/27

    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

    Data latch programming algorithm for multi-bit-per-cell memory devices
    9.
    发明授权
    Data latch programming algorithm for multi-bit-per-cell memory devices 有权

    公开(公告)号：US12230335B2

    公开(公告)日：2025-02-18

    申请号：US17838717

    申请日：2022-06-13

    Applicant: SanDisk Technologies LLC

    Inventor： Toru Miwa ,  Fumiaki Toyama

    IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

    Abstract: A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to receive and store program page data and utilizing a second data latch to store bit information indicating which cells are to be targeted for the multi-stage programming. At each program stage, a respective program loop may be performed with respect to each threshold voltage distribution generated during a prior program stage to create two new threshold voltage distributions from the prior distribution.

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