公开(公告)号：US09721663B1

公开(公告)日：2017-08-01

申请号：US15046740

申请日：2016-02-18

申请人： SANDISK TECHNOLOGIES INC.

发明人： Hiroyuki Ogawa ,  Fumiaki Toyama ,  Takuya Ariki

IPC分类号： G11C16/04 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528

CPC分类号： G11C16/08 ,  G11C5/025 ,  G11C8/10 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

公开(公告)号：US09595535B1

公开(公告)日：2017-03-14

申请号：US15046780

申请日：2016-02-18

申请人： SANDISK TECHNOLOGIES INC.

发明人： Hiroyuki Ogawa ,  Makoto Yoshida ,  Kazutaka Yoshizawa ,  Takuya Ariki ,  Toru Miwa

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11582 ,  G11C8/08 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.

摘要翻译： 用于三维存储器件的字线解码器电路中的字线切换可以被形成为覆盖接触通孔结构的直线场效应晶体管至用于字线的导电层。 覆盖在导电层的阶梯表面上的电介质材料部分中的通孔可以用导电材料填充并凹入以形成接触通孔结构。 在凹部中形成下部有源区后，可以形成栅极并图案化以在覆盖接触通孔结构的区域中形成开口。 可以在开口的侧壁上形成栅极电介质，并且可以在栅电极的开口内部形成晶体管沟道。 上部有源区可以形成在晶体管通道上。