公开(公告)号：US12205658B2

公开(公告)日：2025-01-21

申请号：US17509411

申请日：2021-10-25

Applicant: SanDisk Technologies LLC

Inventor： Shantanu Gupta ,  Amiya Banerjee ,  Harish Singidi

IPC: G11C16/10 ,  G11C7/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.

公开(公告)号：US20230129097A1

公开(公告)日：2023-04-27

申请号：US17509411

申请日：2021-10-25

Applicant: SanDisk Technologies LLC

Inventor： Shantanu Gupta ,  Amiya Banerjee ,  Harish Singidi

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C7/10

Abstract: Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.

公开(公告)号：US11854611B2

公开(公告)日：2023-12-26

申请号：US17326417

申请日：2021-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Harish Singidi ,  Amiya Banerjee ,  Shantanu Gupta

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  H10B41/27 ,  H10B43/27

Abstract: A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.

公开(公告)号：US20220375513A1

公开(公告)日：2022-11-24

申请号：US17326417

申请日：2021-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Harish Singidi ,  Amiya Banerjee ,  Shantanu Gupta

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

Abstract: A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.