公开(公告)号：US11854611B2

公开(公告)日：2023-12-26

申请号：US17326417

申请日：2021-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Harish Singidi ,  Amiya Banerjee ,  Shantanu Gupta

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  H10B41/27 ,  H10B43/27

Abstract: A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.

公开(公告)号：US20220375513A1

公开(公告)日：2022-11-24

申请号：US17326417

申请日：2021-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Harish Singidi ,  Amiya Banerjee ,  Shantanu Gupta

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

Abstract: A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.

公开(公告)号：US10776277B2

公开(公告)日：2020-09-15

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16 ,  G11C16/08 ,  G11C5/02 ,  G11C16/10 ,  G11C8/06 ,  G11C7/10

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US10242750B2

公开(公告)日：2019-03-26

申请号：US15610119

申请日：2017-05-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Shantanu Gupta ,  Avinash Rajagiri ,  Dongxiang Liao ,  Jagdish Sabde ,  Rajan Paudel

IPC: G11C29/12 ,  G11C7/10 ,  G11C7/22

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

公开(公告)号：US20190130978A1

公开(公告)日：2019-05-02

申请号：US15799666

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj ,  Sukhminder Singh Lobana ,  Shrikar Bhagath

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

公开(公告)号：US20190187553A1

公开(公告)日：2019-06-20

申请号：US15845456

申请日：2017-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel J. Linnen ,  Jianhua Zhu ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G03F1/50

CPC classification number: G03F1/50

Abstract: An apparatus is provided that includes a reticle including a die, the reticle configured to increase a number of partial die that can be successfully used as partially operable die.

公开(公告)号：US20180350445A1

公开(公告)日：2018-12-06

申请号：US15610119

申请日：2017-05-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Shantanu Gupta ,  Avinash Rajagiri ,  Dongxiang Liao ,  Jagdish Sabde ,  Rajan Paudel

IPC: G11C29/12 ,  G11C7/10

CPC classification number: G11C29/1201 ,  G11C7/10 ,  G11C7/22

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

公开(公告)号：US20190129861A1

公开(公告)日：2019-05-02

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16

CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/657 ,  G11C5/02 ,  G11C7/1039 ,  G11C8/06 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C2207/107

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US12205658B2

公开(公告)日：2025-01-21

申请号：US17509411

申请日：2021-10-25

Applicant: SanDisk Technologies LLC

Inventor： Shantanu Gupta ,  Amiya Banerjee ,  Harish Singidi

IPC: G11C16/10 ,  G11C7/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.

公开(公告)号：US20230129097A1

公开(公告)日：2023-04-27

申请号：US17509411

申请日：2021-10-25

Applicant: SanDisk Technologies LLC

Inventor： Shantanu Gupta ,  Amiya Banerjee ,  Harish Singidi

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C7/10

Abstract: Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.