公开(公告)号：US20200227397A1

公开(公告)日：2020-07-16

申请号：US16249423

申请日：2019-01-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shinsuke YADA ,  Masanori TSUTSUMI ,  Sayako NAGAMINE ,  Yuji FUKANO ,  Akio NISHIDA ,  Christopher J. PETTI

IPC: H01L25/18 ,  H01L27/11556 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L29/10 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies. Semiconductor substrates may be removed from each memory die upon bonding to a pre-existing assembly.

公开(公告)号：US20170250224A1

公开(公告)日：2017-08-31

申请号：US15207042

申请日：2016-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Perumal RATNAM ,  Abhijit BANDYOPADHYAY ,  Christopher J. PETTI

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/225 ,  H01L29/10 ,  H01L29/66 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L27/2481 ,  H01L21/225 ,  H01L23/528 ,  H01L27/2454 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66666 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.