公开(公告)号：US20180197988A1

公开(公告)日：2018-07-12

申请号：US15400244

申请日：2017-01-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Perumal RATNAM ,  Christopher PETTI ,  Juan SAENZ ,  Guangle ZHOU ,  Abhijit BANDYOPADHYAY ,  Tanmay KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L23/528 ,  H01L27/24 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L23/5283 ,  H01L27/2454 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78648

Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

公开(公告)号：US20170250224A1

公开(公告)日：2017-08-31

申请号：US15207042

申请日：2016-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Perumal RATNAM ,  Abhijit BANDYOPADHYAY ,  Christopher J. PETTI

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/225 ,  H01L29/10 ,  H01L29/66 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L27/2481 ,  H01L21/225 ,  H01L23/528 ,  H01L27/2454 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66666 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.