公开(公告)号：US20170098655A1

公开(公告)日：2017-04-06

申请号：US15379927

申请日：2016-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiying COSTA ,  Dana LEE ,  Yanli ZHANG ,  Johann ALSMEIER ,  Yingda DONG ,  Akira MATSUDAIRA

IPC: H01L27/11524 ,  H01L29/788 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11556

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.

公开(公告)号：US20220254797A1

公开(公告)日：2022-08-11

申请号：US17169987

申请日：2021-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Dana LEE

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.