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公开(公告)号：US10283708B2
公开(公告)日：2019-05-07
申请号：US15452373
申请日：2017-03-07
发明人： Ming-Che Wu , Deepak Kamalanathan , Juan Saenz , Tanmay Kumar
IPC分类号： H01L45/00 , H01L27/24 , H01L27/105 , G11C13/00 , H01L27/115
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.
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公开(公告)号：US20180261766A1
公开(公告)日：2018-09-13
申请号：US15452373
申请日：2017-03-07
发明人： Ming-Che Wu , Deepak Kamalanathan , Juan Saenz , Tanmay Kumar
CPC分类号： H01L45/1608 , G11C7/18 , G11C8/14 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/16
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.
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公开(公告)号：US10388870B2
公开(公告)日：2019-08-20
申请号：US15793247
申请日：2017-10-25
发明人： Perumal Ratnam , Tanmay Kumar , Christopher Petti
摘要： Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.
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公开(公告)号：US10340449B2
公开(公告)日：2019-07-02
申请号：US15611029
申请日：2017-06-01
发明人： Ming-Che Wu , Alvaro Padilla , Tanmay Kumar
摘要： A resistive memory device, such as a BMC ReRAM device, includes at least one resistive memory element which contains a carbon barrier material portion and a resistive memory material portion that is disposed between a first electrode and a second electrode.
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公开(公告)号：US20180166559A1
公开(公告)日：2018-06-14
申请号：US15376916
申请日：2016-12-13
发明人： Guangle Zhou , Chuanbin Pan , Juan Saenz , Tanmay Kumar
IPC分类号： H01L29/66 , H01L27/11521 , H01L27/11568 , H01L27/11556 , H01L27/11582 , H01L27/24 , H01L45/00
CPC分类号： H01L29/66666 , H01L27/11556 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/7827 , H01L45/04 , H01L45/12 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, the word line including a first portion including a first conductive material and a second portion including a second conductive material, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, the semiconductor material layer disposed adjacent the second portion of the word line, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line.
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公开(公告)号：US09953697B2
公开(公告)日：2018-04-24
申请号：US15251818
申请日：2016-08-30
发明人： Tanmay Kumar , Alper Ilkbahar
IPC分类号： G11C11/4091 , H01L45/00 , H01L27/24 , G11C13/00
CPC分类号： G11C11/4091 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C2013/0045 , G11C2213/15 , G11C2213/71 , H01L27/249 , H01L45/08 , H01L45/12 , H01L45/1226 , H01L45/146
摘要： A volatile resistive memory device includes a resistive memory element including a barrier material portion and a charge-modulated resistive memory material portion. The barrier material portion includes a material selected from germanium and a silicon-germanium alloy, and the charge-modulated resistive memory material portion includes a non-filamentary, electrically conductive metal oxide. The resistive memory device may be a volatile eDRAM device. In operation, reading a resistance state of the resistive memory element does not disturb the resistance state of the charge-modulated resistive memory material portion.
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公开(公告)号：US09768180B1
公开(公告)日：2017-09-19
申请号：US15338372
申请日：2016-10-29
发明人： Guangle Zhou , Yubao Li , Yangyin Chen , Tanmay Kumar
IPC分类号： H01L21/00 , H01L27/115 , H01L21/8234 , H01L21/306
CPC分类号： H01L27/11582
摘要： A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.
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公开(公告)号：US20180247975A1
公开(公告)日：2018-08-30
申请号：US15441284
申请日：2017-02-24
发明人： Juan Saenz , Deepak Kamalanathan , Guangle Zhou , Ming-Che Wu , Tanmay Kumar
CPC分类号： H01L27/249 , H01L27/2454 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/1683
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.
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公开(公告)号：US20190123276A1
公开(公告)日：2019-04-25
申请号：US15793247
申请日：2017-10-25
发明人： Perumal Ratnam , Tanmay Kumar , Christopher Petti
CPC分类号： H01L45/1608 , G11C13/0009 , H01L27/2472 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/141 , H01L45/146 , H01L45/16 , H01L45/1683
摘要： Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.
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公开(公告)号：US10109680B1
公开(公告)日：2018-10-23
申请号：US15622100
申请日：2017-06-14
摘要： A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.
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