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    Methods and apparatus for three-dimensional nonvolatile memory
    1.
    发明授权
    Methods and apparatus for three-dimensional nonvolatile memory 有权

    公开(公告)号：US10283708B2

    公开(公告)日：2019-05-07

    申请号：US15452373

    申请日：2017-03-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Ming-Che Wu ,  Deepak Kamalanathan ,  Juan Saenz ,  Tanmay Kumar

    IPC: H01L45/00 ,  H01L27/24 ,  H01L27/105 ,  G11C13/00 ,  H01L27/115

    Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.

    Barrier modulated cell structures with intrinsic vertical bit line architecture
    3.
    发明授权
    Barrier modulated cell structures with intrinsic vertical bit line architecture 有权

    公开(公告)号：US10388870B2

    公开(公告)日：2019-08-20

    申请号：US15793247

    申请日：2017-10-25

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Perumal Ratnam ,  Tanmay Kumar ,  Christopher Petti

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.

    Methods and apparatus for three-dimensional nonvolatile memory
    7.
    发明授权
    Methods and apparatus for three-dimensional nonvolatile memory 有权

    公开(公告)号：US09768180B1

    公开(公告)日：2017-09-19

    申请号：US15338372

    申请日：2016-10-29

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Guangle Zhou ,  Yubao Li ,  Yangyin Chen ,  Tanmay Kumar

    IPC: H01L21/00 ,  H01L27/115 ,  H01L21/8234 ,  H01L21/306

    CPC classification number: H01L27/11582

    Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

    Methods and apparatus for three-dimensional nonvolatile memory
    10.
    发明授权
    Methods and apparatus for three-dimensional nonvolatile memory 有权

    公开(公告)号：US10109680B1

    公开(公告)日：2018-10-23

    申请号：US15622100

    申请日：2017-06-14

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Sebastian J. M. Wicklein ,  Juan P. Saenz ,  Srikanth Ranganathan ,  Ming-Che Wu ,  Tanmay Kumar

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.

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