公开(公告)号：US11894037B2

公开(公告)日：2024-02-06

申请号：US17718759

申请日：2022-04-12

Applicant: SanDisk Technologies LLC

Inventor： Michael Grobis ,  James W. Reiner ,  Michael Nicolas Albert Tran ,  Juan P. Saenz ,  Gerrit Jan Hemink

IPC: G11C13/00 ,  G11C11/16 ,  G11C7/20 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: G11C11/1659 ,  G11C7/20 ,  G11C13/003 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.

公开(公告)号：US20190088323A1

公开(公告)日：2019-03-21

申请号：US15706562

申请日：2017-09-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Emmanuelle Merced-Grafals ,  Juan P. Saenz

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/00 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146

Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.

公开(公告)号：US09748479B2

公开(公告)日：2017-08-29

申请号：US15420595

申请日：2017-01-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Juan P. Saenz ,  Christopher J. Petti

IPC: G11C11/00 ,  H01L45/00 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L45/1233 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608

Abstract: A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

公开(公告)号：US20170141304A1

公开(公告)日：2017-05-18

申请号：US15420595

申请日：2017-01-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Juan P. Saenz ,  Christopher J. Petti

IPC: H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L45/1233 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608

Abstract: A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

公开(公告)号：US20240321371A1

公开(公告)日：2024-09-26

申请号：US18355357

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Deniz Bozdag ,  Juan P. Saenz ,  Dimitri Houssameddine ,  Mark Lin

IPC: G11C17/16 ,  G11C17/18 ,  H10B20/25

CPC classification number: G11C17/165 ,  G11C17/18 ,  H10B20/25

Abstract: An apparatus is provided that includes a memory cell having a reversible resistance-switching memory element coupled in series with a selector element. The selector element has a first resistance. The resistance-switching memory element is configured to reversibly switch between a second resistance and a third resistance. The memory cell may be selectively configured as either a re-writeable memory cell or a one-time programmable memory cell. The memory cell functions as a one-time programmable memory cell regardless of whether the resistance-switching memory element has the second resistance, the third resistance, or is electrically shorted.

公开(公告)号：US20230326506A1

公开(公告)日：2023-10-12

申请号：US17718759

申请日：2022-04-12

Applicant: SanDisk Technologies LLC

Inventor： Michael Grobis ,  James W. Reiner ,  Michael Nicolas Albert Tran ,  Juan P. Saenz ,  Gerrit Jan Hemink

IPC: G11C11/16 ,  G11C7/20 ,  G11C13/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C11/1659 ,  G11C7/20 ,  G11C13/003 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.

公开(公告)号：US10354724B2

公开(公告)日：2019-07-16

申请号：US15706562

申请日：2017-09-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Emmanuelle Merced-Grafals ,  Juan P. Saenz

IPC: G11C11/00 ,  G11C13/00

Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.

公开(公告)号：US10109680B1

公开(公告)日：2018-10-23

申请号：US15622100

申请日：2017-06-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sebastian J. M. Wicklein ,  Juan P. Saenz ,  Srikanth Ranganathan ,  Ming-Che Wu ,  Tanmay Kumar

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.

公开(公告)号：US20180277208A1

公开(公告)日：2018-09-27

申请号：US15714463

申请日：2017-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepak Kamalanathan ,  Juan P. Saenz ,  Tanmay Kumar ,  Emmanuelle Merced-Grafals ,  Sebastian J. M. Wicklein

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/5664 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2213/54 ,  G11C2213/71 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: A memory device is provided that includes a memory controller coupled to a memory cell including a barrier modulated switching structure. The memory controller is adapted to program the memory cell to a first programming state, and program the memory cell to one of a plurality of target programming states from the first programming state.