公开(公告)号：US20220028879A1

公开(公告)日：2022-01-27

申请号：US16934445

申请日：2020-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo MOCHIZUKI ,  Yasuo KASAGI ,  Michiaki SANO ,  Junji OH ,  Yujin TERASAWA ,  Hiroaki NAMBA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/1157

Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers. Contact via structures can be formed in the via cavities by depositing at least one conductive material therein.

公开(公告)号：US20240243061A1

公开(公告)日：2024-07-18

申请号：US18355765

申请日：2023-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takumi MORIYAMA ,  Junji OH ,  Masanori TSUTSUMI

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Memory stack structures including electrically floating vertical semiconductor channels can vertically extend through an alternating stack of insulating layers and electrically conductive layers. Metal interconnect structures connected to the electrically floating vertical semiconductor channels can be temporarily electrically grounded by a connection via structure that contacts a semiconducting or conductive carrier substrate, which is subsequently removed. The conductive via structure may be formed through the alternating stack, through a vertical stack of dielectric material plates and the insulating layers, or through a dielectric material portion. The conductive via structure may be connected to at least one bit line. In case the conductive via structure is temporarily connected to a plurality bit lines, the conductive via structure can be subsequently isolated from the bit lines.