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    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES FOR AND METHOD OF MAKING THE SAME
    1.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES FOR AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20220189872A1

    公开(公告)日：2022-06-16

    申请号：US17684922

    申请日：2022-03-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Michiaki SANO ,  Koichi ITO

    IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/528

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and an insulating spacer laterally surrounding the contact via structure and having an outer surface having a corrugated vertical cross-sectional profile in which first portions of the insulating spacer located at levels of the electrically conductive layers laterally protrude outward relative to second portions of the insulating spacer located at levels of the insulating layers.

    THREE-DIMENSIONAL MEMORY DEVICE WITH COMPOSITE CHARGE STORAGE STRUCTURES AND METHODS FOR FORMING THE SAME
    3.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH COMPOSITE CHARGE STORAGE STRUCTURES AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20210257378A1

    公开(公告)日：2021-08-19

    申请号：US16794536

    申请日：2020-02-19

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yu UEDA ,  Michiaki SANO

    IPC: H01L27/11582 ,  H01L27/11565

    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

    THREE-DIMENSIONAL MEMORY DEVICE WITH PUNCH-THROUGH-RESISTANT WORD LINES AND METHODS FOR FORMING THE SAME
    5.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH PUNCH-THROUGH-RESISTANT WORD LINES AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20220028879A1

    公开(公告)日：2022-01-27

    申请号：US16934445

    申请日：2020-07-21

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Ryo MOCHIZUKI ,  Yasuo KASAGI ,  Michiaki SANO ,  Junji OH ,  Yujin TERASAWA ,  Hiroaki NAMBA

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/1157

    Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers. Contact via structures can be formed in the via cavities by depositing at least one conductive material therein.

    SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING
    7.
    发明公开
    SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING 审中-公开

    公开(公告)号：US20240096695A1

    公开(公告)日：2024-03-21

    申请号：US17932907

    申请日：2022-09-16

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Michiaki SANO ,  Tatsuya HINOUE

    IPC: H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76843

    Abstract: A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES AND METHOD OF MAKING THE SAME (AS AMENDED)
    8.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES AND METHOD OF MAKING THE SAME (AS AMENDED) 有权

    公开(公告)号：US20220328413A1

    公开(公告)日：2022-10-13

    申请号：US17807804

    申请日：2022-06-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Tomohiro KUBO ,  Michiaki SANO

    IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region that is located adjacent to the memory array region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and a dielectric spacer laterally surrounding the contact via structure. Each contact via structure other than a contact via structure contacting a topmost one of the electrically conductive layers extends through and is laterally surrounded by each electrically conductive layer that overlies the respective electrically conductive layer.

    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A REPLACEMENT BURIED SOURCE LINE AND METHODS OF MAKING THE SAME
    9.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A REPLACEMENT BURIED SOURCE LINE AND METHODS OF MAKING THE SAME 审中-公开

    公开(公告)号：US20200219895A1

    公开(公告)日：2020-07-09

    申请号：US16241171

    申请日：2019-01-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Mitsuteru MUSHIGA ,  Kenji SUGIURA ,  Akio NISHIDA ,  Ryosuke KANEKO ,  Michiaki SANO

    IPC: H01L27/11582 ,  H01L21/8234

    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

    MULTIHEIGHT CONTACT VIA STRUCTURES FOR A MULTILEVEL INTERCONNECT STRUCTURE
    10.
    发明申请
    MULTIHEIGHT CONTACT VIA STRUCTURES FOR A MULTILEVEL INTERCONNECT STRUCTURE 有权
    多层互连结构的多层结构联系

    公开(公告)号：US20160322374A1

    公开(公告)日：2016-11-03

    申请号：US15211401

    申请日：2016-07-15

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Michiaki SANO ,  Keisuke IZUMI

    IPC: H01L27/115 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/522

    CPC classification number: H01L27/11556 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.

    Abstract translation: 可以在半导体衬底上形成凹陷区域，并且可以在半导体衬底的凹入的水平表面上形成外围半导体器件。 绝缘层和牺牲材料层的交替叠层形成在半导体衬底之上，并且通过其形成存储器堆叠结构。 延伸到位于不同深度处的牺牲材料层的接触开口可以通过在掩模层上迭代地修剪减薄层的顺序曝光掩模层中的更多数量的开口，以及将预先存在的接触开口 一级 延伸到位于不同级别的导电电极的导电通孔结构可以设置有自对准的绝缘衬垫。

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