公开(公告)号：US20240243061A1

公开(公告)日：2024-07-18

申请号：US18355765

申请日：2023-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takumi MORIYAMA ,  Junji OH ,  Masanori TSUTSUMI

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Memory stack structures including electrically floating vertical semiconductor channels can vertically extend through an alternating stack of insulating layers and electrically conductive layers. Metal interconnect structures connected to the electrically floating vertical semiconductor channels can be temporarily electrically grounded by a connection via structure that contacts a semiconducting or conductive carrier substrate, which is subsequently removed. The conductive via structure may be formed through the alternating stack, through a vertical stack of dielectric material plates and the insulating layers, or through a dielectric material portion. The conductive via structure may be connected to at least one bit line. In case the conductive via structure is temporarily connected to a plurality bit lines, the conductive via structure can be subsequently isolated from the bit lines.

公开(公告)号：US20240260266A1

公开(公告)日：2024-08-01

申请号：US18356896

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Shunsuke TAKUMA ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Takashi KASHIMURA ,  Tomohiro KUBO ,  Hisakazu OTOI ,  Hiroyuki TANAKA ,  Takumi MORIYAMA ,  Ryota SUZUKI

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

公开(公告)号：US20220344365A1

公开(公告)日：2022-10-27

申请号：US17237476

申请日：2021-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki FUJIMURA ,  Satoshi SHIMIZU ,  Takumi MORIYAMA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

公开(公告)号：US20240363165A1

公开(公告)日：2024-10-31

申请号：US18630482

申请日：2024-04-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kento SAKANE ,  Masanori TSUTSUMI ,  Hiroyuki TANAKA ,  Naohiro HOSODA ,  Takumi MORIYAMA

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.

公开(公告)号：US20240260267A1

公开(公告)日：2024-08-01

申请号：US18356919

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Naohiro HOSODA ,  Takumi MORIYAMA ,  Ryota SUZUKI ,  Takashi KUDO ,  Nobuyuki FUJIMURA

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A method of making a memory device includes forming an alternating stack of insulating layers and sacrificial material layers, where a silicon oxycarbide liner is interposed between a first sacrificial material layer and a first insulating layer, and the first sacrificial material layer is direct contact with a second insulating layer or a dielectric material layer composed of a silicon oxide material, forming a memory opening through the alternating stack, forming a memory opening fill structure in the memory opening, forming backside recesses by removing the sacrificial material layers selective to the silicon oxycarbide liner, and forming electrically conductive layers in the backside recesses.

公开(公告)号：US20210036004A1

公开(公告)日：2021-02-04

申请号：US16583906

申请日：2019-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takumi MORIYAMA ,  Yasushi DOWAKI ,  Yuki KASAI ,  Satoshi SHIMIZU ,  Jayavel PACHAMUTHU

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.