公开(公告)号：US20220028879A1

公开(公告)日：2022-01-27

申请号：US16934445

申请日：2020-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo MOCHIZUKI ,  Yasuo KASAGI ,  Michiaki SANO ,  Junji OH ,  Yujin TERASAWA ,  Hiroaki NAMBA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/1157

Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers. Contact via structures can be formed in the via cavities by depositing at least one conductive material therein.

公开(公告)号：US20180151589A1

公开(公告)日：2018-05-31

申请号：US15843659

申请日：2017-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Satoshi SHIMIZU ,  Hiroyuki OGAWA ,  Yasuo KASAGI ,  Kento KITAMURA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/792 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.

公开(公告)号：US20180122906A1

公开(公告)日：2018-05-03

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Kento KITAMURA ,  Tong ZHANG ,  Chun GE ,  Yanli ZHANG ,  Satoshi SHIMIZU ,  Yasuo KASAGI ,  Hiroyuki OGAWA ,  Daxin MAO ,  Kensuke YAMAGUCHI ,  Johann ALSMEIER ,  James KAI

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.