公开(公告)号：US20180307503A1

公开(公告)日：2018-10-25

申请号：US15496490

申请日：2017-04-25

Applicant: SanDisk Technologies LLC

Inventor： Uri Peltz ,  Amir Hadar ,  Mark Shlick ,  Mark Murin

IPC: G06F9/44 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F9/4418 ,  G06F12/0246 ,  G06F13/161 ,  G06F13/1673 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: A device or apparatus may be configured to perform memory operations on a memory die while a current multi-level cell programming operation is being performed. In the event that a controller identifies pending memory operations to be performed in the memory die, the controller may communicate with the memory die to determine a status of auxiliary latches of the memory die. Depending on the status, the controller may determine if the memory die is in a suspend/resume period and/or which pending memory operations to have performed.

公开(公告)号：US20240257878A1

公开(公告)日：2024-08-01

申请号：US18355352

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Mark Shlick ,  Shemmer Choresh

IPC: G11C16/14 ,  G11C5/14 ,  G11C16/32

CPC classification number: G11C16/14 ,  G11C5/145 ,  G11C16/32

Abstract: An apparatus is provided that includes a plurality of non-volatile memory cells, a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells, and a control circuit coupled to the non-volatile memory cells and the charge pump circuit. The control circuit is configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal depending on a memory operation being performed on the non-volatile memory cells.

公开(公告)号：US11373710B1

公开(公告)日：2022-06-28

申请号：US17165703

申请日：2021-02-02

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Yu-Chung Lien ,  Mark Murin ,  Mark Shlick

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/08 ,  G11C8/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/10

Abstract: Time division peak power management in non-volatile memory systems is disclosed. The memory system has a memory controller and a number of semiconductor dies. Each die is assigned a time slot in which to perform high current portions of memory operations. The memory controller provides an external clock to each die. Each die tracks repeating time slots based on the external clock. The memory controller may synchronize this tracking. If a die is about to perform a high current portion of a memory operation, the die checks to determine if its allocated slot has been reached. If not, the die halts the memory operation until its allocated time slot is reached. When the allocated time slot is reached, the halted memory operation is resumed at the high current portion. Therefore, the high current portion of the memory operation occurs during the allocated time slot.

公开(公告)号：US20240355400A1

公开(公告)日：2024-10-24

申请号：US18346347

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Mark Shlick ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/32

Abstract: To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.

公开(公告)号：US10360045B2

公开(公告)日：2019-07-23

申请号：US15496490

申请日：2017-04-25

Applicant: SanDisk Technologies LLC

Inventor： Uri Peltz ,  Amir Hadar ,  Mark Shlick ,  Mark Murin

IPC: G06F9/4401 ,  G06F12/02 ,  G06F13/16

Abstract: A device or apparatus may be configured to perform memory operations on a memory die while a current multi-level cell programming operation is being performed. In the event that a controller identifies pending memory operations to be performed in the memory die, the controller may communicate with the memory die to determine a status of auxiliary latches of the memory die. Depending on the status, the controller may determine if the memory die is in a suspend/resume period and/or which pending memory operations to have performed.

公开(公告)号：US10162538B2

公开(公告)日：2018-12-25

申请号：US14871262

申请日：2015-09-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mark Shlick ,  Refael Ben-Rubi ,  Uri Shir ,  Ahiad Turgeman ,  Uri Peltz

IPC: G06F3/06 ,  G11C29/04

Abstract: A data storage device includes a controller and a memory. The memory is coupled to the controller. The memory includes storage elements coupled to bit lines. The controller is configured to access bit line integrity data corresponding to a region of the memory, the bit line integrity data indicating a number of bit lines. The controller is also configured to store data related to a memory operation threshold based on the number of bit lines.