公开(公告)号：US20170148809A1

公开(公告)日：2017-05-25

申请号：US15219719

申请日：2016-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Masafumi MIYAMOTO ,  Hiroyuki OGAWA

IPC: H01L27/115 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847

Abstract: Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.

公开(公告)号：US20170148808A1

公开(公告)日：2017-05-25

申请号：US15219652

申请日：2016-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Masafumi MIYAMOTO ,  James KAI

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/311 ,  H01L23/528 ,  H01L21/28 ,  H01L29/08 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847

Abstract: An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an etchant to remove the sacrificial material layers to form lateral recesses and to provide a reactant for depositing electrically conductive layers in the lateral recesses. By distributing the access openings across the entirety of the openings and eliminating the need to employ backside trenches for replacement of the sacrificial material layers, the size and lateral extent of backside trenches can be reduced to a level sufficient to accommodate only backside contact via structures.