公开(公告)号：US20220399448A1

公开(公告)日：2022-12-15

申请号：US17348328

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuhiro TOGO ,  Jun AKAIWA ,  Hiroshi NAKATSUJI ,  Masashi ISHIDA

IPC: H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

公开(公告)号：US20240250119A1

公开(公告)日：2024-07-25

申请号：US18356851

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masashi ISHIDA

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/66659 ,  H01L29/66689

Abstract: A field effect transistor includes a semiconductor channel having a doping of a first conductivity type, a gate structure overlying the semiconductor channel, a source region and a drain region, a source-side extension region including a source-side-extension plate portion and source-side-extension rail portions that overlie the source-side-extension plate portion, source-side counter-doped rails having a doping of the first conductivity type, a drain-side extension region including a drain-side-extension plate portion and drain-side-extension rail portions that overlie the drain-side-extension plate portion, and drain-side counter-doped rails interlaced with the drain-side-extension rail portions. A first superjunction structure is provided between the source-side counter-doped rails and the source-side extension region. A second superjunction structure is provided between the drain-side counter-doped rails and the drain-side extension region.

公开(公告)号：US20220399447A1

公开(公告)日：2022-12-15

申请号：US17348305

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jun AKAIWA ,  Hiroshi NAKATSUJI ,  Masashi ISHIDA

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/45 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

公开(公告)号：US20220278209A1

公开(公告)日：2022-09-01

申请号：US17188271

申请日：2021-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruyuki MINE ,  Hiroyuki OGAWA ,  Masashi ISHIDA

IPC: H01L29/417 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/08

Abstract: A semiconductor structure includes a high voltage field effect transistor having metal-insulator-semiconductor active region contact structures and a low voltage field effect transistor having metal-semiconductor active region contact structures, and at least one of a smaller gate dielectric thickness or a smaller gate length than the high voltage field effect transistor.