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    GATE MATERIAL-BASED CAPACITOR AND RESISTOR STRUCTURES AND METHODS OF FORMING THE SAME
    1.
    发明申请
    GATE MATERIAL-BASED CAPACITOR AND RESISTOR STRUCTURES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220068915A1

    公开(公告)日：2022-03-03

    申请号：US17006265

    申请日：2020-08-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Hokuto KODATE ,  Hiroyuki OGAWA ,  Dai IWATA ,  Mitsuhiro TOGO

    IPC: H01L27/06 ,  H01L21/8234

    Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.

    HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME
    2.
    发明申请
    HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20220109054A1

    公开(公告)日：2022-04-07

    申请号：US17063084

    申请日：2020-10-05

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Mitsuhiro TOGO

    IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40

    Abstract: A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.

    FIELD EFFECT TRANSISTORS WITH GATE FINS AND METHOD OF MAKING THE SAME
    4.
    发明申请
    FIELD EFFECT TRANSISTORS WITH GATE FINS AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20230082824A1

    公开(公告)日：2023-03-16

    申请号：US17562635

    申请日：2021-12-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Srinivas PULUGURTHA ,  Yanli ZHANG ,  Johann ALSMEIER ,  Mitsuhiro TOGO

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

    TRANSISTORS WITH STEPPED CONTACT VIA STRUCTURES AND METHODS OF FORMING THE SAME
    7.
    发明申请
    TRANSISTORS WITH STEPPED CONTACT VIA STRUCTURES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220416037A1

    公开(公告)日：2022-12-29

    申请号：US17362121

    申请日：2021-06-29

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Mitsuhiro TOGO ,  Hiroshi NAKATSUJI

    IPC: H01L29/417 ,  H01L29/40

    Abstract: A transistor includes a semiconductor substrate including a first active region, a second active region, and a semiconductor channel, a gate stack structure that overlies the semiconductor channel, a proximal dielectric material layer overlying the semiconductor substrate, laterally surrounding the gate stack structure, a distal dielectric material layer overlying the proximal dielectric material layer, and a first contact via structure contacting the first active region having a greater lateral extent at a level of the proximal dielectric material layer than at a level of the distal dielectric material layer.

    HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME
    9.
    发明申请
    HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20220109071A1

    公开(公告)日：2022-04-07

    申请号：US17063145

    申请日：2020-10-05

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Mitsuhiro TOGO

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

    Abstract: A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.

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