公开(公告)号：US10217746B1

公开(公告)日：2019-02-26

申请号：US15867881

申请日：2018-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tae-Kyung Kim ,  Raghuveer S. Makala ,  Yanli Zhang ,  Hiroyuki Kinoshita ,  Daxin Mao ,  Jixin Yu ,  Yiyang Gong ,  Kazuto Watanabe ,  Michiaki Sano ,  Haruki Urata ,  Akira Takahashi

IPC: H01L27/105 ,  H01L21/768 ,  H01L27/24 ,  H01L23/535 ,  H01L45/00

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electrically conductive layers.

公开(公告)号：US10937800B2

公开(公告)日：2021-03-02

申请号：US16352157

申请日：2019-03-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tae-Kyung Kim ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/11556 ,  H01L29/10

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures located within a respective one of the memory openings. A multi-pillared dielectric isolation structure extends through upper sections of a neighboring pair of memory openings. The multi-pillared dielectric isolation structure includes a plurality of dielectric pillar portions located within a respective one of the memory openings, and at least one horizontally-extending portion adjoining each of the plurality of dielectric pillar portions and located between a vertically neighboring pair of insulating layers within the alternating stack. The at least one horizontally-extending portion laterally separates laterally neighboring strips of at least one electrically conductive layer within the alternating stack.

公开(公告)号：US10825826B2

公开(公告)日：2020-11-03

申请号：US16889030

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/06 ,  G11C5/02

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US20200295029A1

公开(公告)日：2020-09-17

申请号：US16889030

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US10707228B2

公开(公告)日：2020-07-07

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/088 ,  H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US20200066745A1

公开(公告)日：2020-02-27

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/06 ,  G11C5/02

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US10211215B1

公开(公告)日：2019-02-19

申请号：US15895102

申请日：2018-02-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yashushi Ishii ,  Kazuto Watanabe ,  Michiaki Sano ,  Haruki Urata ,  Akira Takahashi ,  Tae-Kyung Kim

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11597 ,  H01L27/28 ,  H01L27/11529 ,  H01L27/105 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11514 ,  H01L45/00

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Each of the first insulating layers and the first sacrificial material layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion. Memory stack structures are formed through the horizontally-extending portions of the alternating stack. Regions of the non-horizontally-extending portions of the sacrificial material layers are masked with patterned etch mask portions. Unmasked first regions of the non-horizontally-extending portions of the first sacrificial material layers are selectively recessed, and the sacrificial material layers with electrically conductive layers. Each electrically conductive layer can include a vertical plate region and a protrusion region that protrudes above the vertical plate region and having a narrower lateral dimension that the vertical plate region. Metal contact structures can be formed on the protrusion regions without contacting the vertical plate regions.