公开(公告)号：US11968825B2

公开(公告)日：2024-04-23

申请号：US17126504

申请日：2020-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhen Chen ,  Yanli Zhang

IPC: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures including a respective vertical semiconductor channel and a respective memory film vertically extend through the alternating stack and the vertical layer stack. Each of the vertical semiconductor channels includes a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack.

公开(公告)号：US10553599B1

公开(公告)日：2020-02-04

申请号：US16142875

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhen Chen ,  Michiaki Sano ,  Mitsuteru Mushiga

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11565 ,  H01L21/311

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective memory-level semiconductor channel and a respective memory film. Drain-select-level gate electrodes overlie the alternating stack. Drain-select-level pillar structures extend through a respective one of the drain-select-level gate electrodes. Each drain-select-level semiconductor channel is electrically connected to an underlying one of the memory-level semiconductor channels. A planar insulating spacer layer having a homogeneous composition throughout directly contacts top surfaces of the memory films and bottom surfaces of the drain-select-level gate electrodes.

公开(公告)号：US10290803B2

公开(公告)日：2019-05-14

申请号：US15367791

申请日：2016-12-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Zhen Chen ,  Tetsuya Yamada ,  Akira Nakada ,  Yasuke Oda ,  Manabu Hayashi ,  Shigenori Sato

IPC: H01L27/115 ,  H01L27/24 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.

公开(公告)号：US10290681B2

公开(公告)日：2019-05-14

申请号：US15711075

申请日：2017-09-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chao Feng Yeh ,  Jongsun Sel ,  Zhen Chen

IPC: H01L29/792 ,  H01L27/24 ,  H01L45/00

Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.