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    Array of hole-type surround gate vertical field effect transistors and method of making thereof
    2.
    发明授权
    Array of hole-type surround gate vertical field effect transistors and method of making thereof 有权

    公开(公告)号：US10290681B2

    公开(公告)日：2019-05-14

    申请号：US15711075

    申请日：2017-09-21

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Chao Feng Yeh ,  Jongsun Sel ,  Zhen Chen

    IPC: H01L29/792 ,  H01L27/24 ,  H01L45/00

    Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.

    Memory device containing wrap gate vertical select transistors and method of making thereof
    6.
    发明授权
    Memory device containing wrap gate vertical select transistors and method of making thereof 有权

    公开(公告)号：US10079267B1

    公开(公告)日：2018-09-18

    申请号：US15632773

    申请日：2017-06-26

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Chao Feng Yeh ,  Tian Chen Dong

    IPC: H01L29/06 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2454 ,  H01L27/249 ,  H01L45/16

    Abstract: A gate dielectric layer and a gate electrode layer are formed around semiconductor pillars. The gate electrode layer is patterned to remove top portions that protrude above the semiconductor pillars and divided into multiple strips. Each strip constitutes a gate electrode line including a horizontal layer portion and a plurality of surrounding portions that entirely laterally surround respective channel regions of the semiconductor pillars to form wrap gate vertical select field effect transistors. Vertical stacks of memory elements and alternating layer stacks including a vertically alternating sequence of insulating strips and electrically conductive word line strips are formed above the vertical field effect transistors. Vertical bit lines can be formed inside the vertical stacks of memory elements.

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