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公开(公告)号：US10748622B2
公开(公告)日：2020-08-18
申请号：US16283464
申请日：2019-02-22
Applicant: SanDisk Technologies LLC
Inventor： Lei Lin , Zhuojie Li , Tai-Yuan Tseng , Henry Chin , Gerrit Jan Hemink
IPC: G11C16/10 , G11C16/04 , G11C16/34 , G11C16/26 , G11C11/56 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.
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公开(公告)号：US10726940B2
公开(公告)日：2020-07-28
申请号：US16239517
申请日：2019-01-03
Applicant: SanDisk Technologies LLC
Inventor： Zhuojie Li , Hua-Ling Cynthia Hsu , Yen-Lung Li , Min Peng
Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.
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Patent Agency Ranking
公开(公告)号：US20200234768A1
公开(公告)日：2020-07-23
申请号：US16283464
申请日：2019-02-22
Applicant: SanDisk Technologies LLC
Inventor： Lei Lin , Zhuojie Li , Tai-Yuan Tseng , Henry Chin , Gerrit Jan Hemink
Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.
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公开(公告)号：US10535401B2
公开(公告)日：2020-01-14
申请号：US16000413
申请日：2018-06-05
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Lei Lin , Zhuojie Li , Henry Chin , Cynthia Hsu
Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.
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公开(公告)号：US11355208B2
公开(公告)日：2022-06-07
申请号：US16916790
申请日：2020-06-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Fanglin Zhang , Zhuojie Li , Huai-Yuan Tseng
IPC: G11C16/06 , G11C16/34 , G11C16/04 , G11C16/10 , H01L27/11582 , G11C16/26 , H01L27/11565 , G11C11/56
Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.
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公开(公告)号：US10971222B2
公开(公告)日：2021-04-06
申请号：US16717532
申请日：2019-12-17
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Lei Lin , Zhuojie Li , Henry Chin , Cynthia Hsu
Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.
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公开(公告)号：US20190371395A1
公开(公告)日：2019-12-05
申请号：US16000413
申请日：2018-06-05
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Lei Lin , Zhuojie Li , Henry Chin , Cynthia Hsu
Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.
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