公开(公告)号：US10748622B2

公开(公告)日：2020-08-18

申请号：US16283464

申请日：2019-02-22

Applicant: SanDisk Technologies LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Tai-Yuan Tseng ,  Henry Chin ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

公开(公告)号：US20200234768A1

公开(公告)日：2020-07-23

申请号：US16283464

申请日：2019-02-22

Applicant: SanDisk Technologies LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Tai-Yuan Tseng ,  Henry Chin ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

公开(公告)号：US10535401B2

公开(公告)日：2020-01-14

申请号：US16000413

申请日：2018-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Henry Chin ,  Cynthia Hsu

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C29/12 ,  G11C16/08

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

公开(公告)号：US10971222B2

公开(公告)日：2021-04-06

申请号：US16717532

申请日：2019-12-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Henry Chin ,  Cynthia Hsu

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C29/12 ,  G11C16/08

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

公开(公告)号：US20190371395A1

公开(公告)日：2019-12-05

申请号：US16000413

申请日：2018-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Henry Chin ,  Cynthia Hsu

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C29/12

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

公开(公告)号：US20210383879A1

公开(公告)日：2021-12-09

申请号：US16893859

申请日：2020-06-05

Applicant: SanDisk Technologies LLC

Inventor： Lei Lin ,  Wei Zhao ,  Henry Chin ,  Yen-Lung Li

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08

Abstract: A memory apparatus and method of operation is provided. The apparatus includes selected memory cells coupled to a selected word line and each storing a threshold voltage representative of a selected cell data programmed in a program-verify operation. Unselected memory cells are coupled to a neighbor word line disposed adjacent the selected word line. A control circuit is coupled to the selected and unselected memory cells and configured to ramp from at least one initial voltage applied to the neighbor word line directly to a target neighbor verify voltage without exceeding or falling below the target neighbor verify voltage thereby assisting the selected word line reach at least one verify reference voltage used in verifying the threshold voltage of the selected memory cells during at least one verify stage of the program-verify operation following a program operation of the program-verify operation.