公开(公告)号：US20150228655A1

公开(公告)日：2015-08-13

申请号：US14617572

申请日：2015-02-09

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi HARADA ,  Masaru AKINO

IPC: H01L27/10 ,  H01L49/02

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: Provided is a semiconductor resistor circuit with high accuracy. An insulating film is formed to cover a plurality of resistor groups having upper portions covered with a plurality of metal wirings. The insulating film has a membrane stress that is higher than that of the metal wirings, and is formed between the metal wirings and the resistor groups.

Abstract translation: 提供了一种高精度的半导体电阻电路。 形成绝缘膜以覆盖多个具有被多个金属布线覆盖的上部的电阻器组。 该绝缘膜的膜应力高于金属布线，并且形成在金属布线和电阻体之间。

公开(公告)号：US20140084378A1

公开(公告)日：2014-03-27

申请号：US14033842

申请日：2013-09-23

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi HARADA ,  Masayuki HASHITANI

IPC: H01L27/092

CPC classification number: H01L27/0883 ,  H01L27/092 ,  H01L29/0615 ,  H01L29/7833

Abstract: Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.

Abstract translation: 提供具有稳定输出电压的恒压电路。 在通过串联连接增强型NMOS和凹陷型NMOS而形成的恒压电路中，为了增强凹陷型NMOS的反向偏置效应，仅在P型阱区域中将杂质浓度设定为高 其上设置有凹陷型NMOS。

公开(公告)号：US20130249119A1

公开(公告)日：2013-09-26

申请号：US13846584

申请日：2013-03-18

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi HARADA

IPC: H01L21/58

CPC classification number: H01L21/58 ,  H01L23/49513 ,  H01L23/4952 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Provided is a semiconductor integrated circuit device having flexible pin arrangement. A semiconductor integrated circuit is bonded to a die pad with an insulating paste, and the potential of the die pad is fixed through a bonding wire from an Al pad provided on the surface of the semiconductor integrated circuit. In the case of a P-type semiconductor substrate, the die pad is set as a terminal other than a terminal having a minimum operating potential of the semiconductor integrated circuit.

Abstract translation: 提供了具有柔性引脚布置的半导体集成电路器件。 利用绝缘膏将半导体集成电路接合到管芯焊盘，并且通过接合线将焊盘的电位从设置在半导体集成电路的表面上的Al焊盘固定。 在P型半导体基板的情况下，将芯片焊盘设定为具有半导体集成电路的最小工作电位的端子以外的端子。

公开(公告)号：US20160033981A1

公开(公告)日：2016-02-04

申请号：US14805550

申请日：2015-07-22

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi HARADA ,  Shinjiro KATO

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G11C5/147

Abstract: Provided is a semiconductor integrated circuit device including a memory element to which a voltage and a current is input via a regulating input terminal to be able to change a threshold voltage thereof. The semiconductor integrated circuit device can change an output voltage depending on the threshold voltage. Also provided is a method of regulating an output voltage of the semiconductor integrated circuit device, including changing an input voltage to the regulating input terminal to change the output voltage, thereby setting an arbitrary output voltage.

Abstract translation: 提供了一种半导体集成电路器件，其包括经由调节输入端子输入电压和电流的存储元件，以能够改变其阈值电压。 半导体集成电路器件可以根据阈值电压改变输出电压。 还提供了一种调节半导体集成电路器件的输出电压的方法，包括改变输入电压到调节输入端以改变输出电压，从而设定任意的输出电压。

公开(公告)号：US20150243650A1

公开(公告)日：2015-08-27

申请号：US14711589

申请日：2015-05-13

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi HARADA

IPC: H01L27/06 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5226 ,  H01L28/20 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a resistance circuit and an insulated gate field effect transistor. The resistance circuit includes a resistance element having a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film of silicon nitride formed on the first thin film so as to be wider than the resistance element, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film and being provided in the intermediate insulating film at a depth reaching the first thin film, and a metal wiring formed in the contact hole. The insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film.

Abstract translation: 半导体器件包括电阻电路和绝缘栅场效应晶体管。 电阻电路包括具有设置在半导体衬底的表面上的隔离氧化膜上的第一薄膜的电阻元件，形成在第一薄膜上的第二氮化硅薄膜比电阻元件宽， 形成在第二薄膜上的中间绝缘膜，穿过第二薄膜的接触孔，并且在到达第一薄膜的深度处设置在中间绝缘膜中，以及形成在接触孔中的金属布线。 绝缘栅场效应晶体管设置在由隔离氧化膜包围的半导体衬底的区域中。

公开(公告)号：US20140217511A1

公开(公告)日：2014-08-07

申请号：US14172217

申请日：2014-02-04

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takashi KATAKURA ,  Hirofumi HARADA ,  Yoshitsugu HIROSE

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/0274 ,  H01L27/0288

Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.

Abstract translation: 提供具有较小面积的ESD保护电路。 ESD保护电路包括：P型扩散电阻器12，其一端连接到形成在N型阱中的输入端子11; 设置在扩散电阻器12和连接到电源端子的N型阱之间的二极管14; 漏极连接到扩散电阻器12的另一端的NMOS晶体管15; 以及形成在电源端子和接地端子之间的寄生二极管。

公开(公告)号：US20140054719A1

公开(公告)日：2014-02-27

申请号：US14073167

申请日：2013-11-06

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi HARADA

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5226 ,  H01L28/20 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a resistance circuit including a resistance element as a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film comprised of silicon nitride formed on the first thin film, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film, and a metal wiring formed on the contract hole. The first thin film has a low concentration impurity region and a high concentration impurity region at each of both ends of the low concentration impurity region. The second thin film is formed on the first thin film so as to be disposed on each of the high concentration impurity regions but not on the low concentration impurity region. An insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film.

Abstract translation: 半导体器件具有电阻电路，该电阻电路包括布置在半导体衬底的表面上的隔离氧化膜上的作为第一薄膜的电阻元件，由第一薄膜上形成的氮化硅构成的第二薄膜，中间绝缘膜 形成在第二薄膜上，穿过第二薄膜的接触孔以及形成在收缩孔上的金属布线。 第一薄膜在低浓度杂质区域的两端各自具有低浓度杂质区和高浓度杂质区。 第二薄膜形成在第一薄膜上，以便设置在每个高浓度杂质区域上，而不是设置在低浓度杂质区域上。 在由隔离氧化膜包围的半导体衬底的区域中提供绝缘栅场效应晶体管。