公开(公告)号：US20150279895A1

公开(公告)日：2015-10-01

申请号：US14666497

申请日：2015-03-24

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takeshi KOYAMA

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/1463

Abstract: Provided is an image sensor having semiconductor light receiving elements configured to prevent carriers generated at a deep position of a Si substrate from affecting an adjacent photodiode due to lateral diffusion (crosstalk between pixels). A modified layer is formed between adjacent photodiodes by a laser to generate a recombination level, to thereby suppress crosstalk between pixels.

Abstract translation: 提供了具有半导体光接收元件的图像传感器，其被配置为防止由于横向扩散（像素之间的串扰）而在Si衬底的深位置产生的载流子影响相邻的光电二极管。 通过激光在相邻的光电二极管之间形成修改层，以产生复合电平，从而抑制像素之间的串扰。

公开(公告)号：US20140138762A1

公开(公告)日：2014-05-22

申请号：US14086177

申请日：2013-11-21

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takeshi KOYAMA ,  Yoshitsugu HIROSE

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L27/0266 ,  H01L23/4824 ,  H01L27/0274 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via (16) is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.

Abstract translation: 提供了具有高ESD耐受性的半导体器件。 第一通孔（16）用于将焊盘电连接到ESD保护电路的NMOS晶体管的漏极。 第一通孔（16）布置在漏极的正上方，并且基本上直接存在于焊盘的正下方。 因此，由ESD引起的并施加到焊盘的浪涌电流更可能在所有漏极中均匀地流动。 然后，ESD保护电路的NMOS晶体管的各个沟道更可能均匀地操作，因此半导体器件的ESD容限增加。

公开(公告)号：US20140117451A1

公开(公告)日：2014-05-01

申请号：US14062019

申请日：2013-10-24

Applicant: Seiko Instruments Inc.

Inventor： Takeshi KOYAMA ,  Yoshitsugu HIROSE

IPC: H01L29/78

CPC classification number: H01L29/41758 ,  H01L23/4824 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad (22) to a drain of an NMOS transistor of an ESD protective circuit. The first vias (16) are formed under the pad (22) only on one side of a rectangular ring-shaped intermediate metal film (17) and on another side thereof opposed to the one side. In other words, all the first vias (16) for establishing an electrical connection to the drains are present substantially directly under the pad (22). Consequently, a surge current caused by ESD and applied to the pad (22) is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protective circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device is increased.

Abstract translation: 提供了具有高ESD耐受性的半导体器件。 第一通孔（16）用于将焊盘（22）电连接到ESD保护电路的NMOS晶体管的漏极。 第一通孔（16）仅在矩形环状中间金属膜（17）的一侧上形成在垫（22）下方，并且在与另一侧相对的另一侧上形成。 换句话说，用于建立到漏极的电连接的所有第一通路（16）基本上直接存在于焊盘（22）的正下方。 因此，由ESD引起的并施加到焊盘（22）的浪涌电流更可能在所有漏极中均匀地流动。 然后，ESD保护电路的NMOS晶体管的各个沟道更可能均匀地工作，因此增加了半导体器件的耐ESD性。

公开(公告)号：US20140217510A1

公开(公告)日：2014-08-07

申请号：US14166937

申请日：2014-01-29

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takeshi KOYAMA ,  Tomomitsu RISAKI

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0277

Abstract: Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.

Abstract translation: 提供了一种使用梳状N型MOS晶体管作为ESD保护元件并能够均匀地操作整个梳状N型MOS晶体管的半导体器件。 通过调整用作ESD保护元件的N型MOS晶体管的栅电极的长度L，该长度L与设置在围绕外周的保护环上的用于固定衬底电位的接触点的距离相应， 表示为梳齿的N型MOS晶体管均匀地进入快速恢复操作，从而避免局部电流集中并获得期望的ESD容限。