公开(公告)号：US20160020200A1

公开(公告)日：2016-01-21

申请号：US14771547

申请日：2014-02-14

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Tomomitsu RISAKI

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/027 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0274 ,  H01L29/41758 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to provide a semiconductor device having a high ESD tolerance, a source wiring (32a) is formed on a gate (31) and a source (32) in a region of an NMOS transistor (30). The source wiring (32a) electrically connects the gate (31), the source (32), and a ground terminal. A drain wiring (33a) is formed on a drain (33) in the region of the NMOS transistor (30) . The drain wiring (33a) electrically connects the drain (33) and a pad (20) serving as an external connection electrode. Moreover, in the region of the NMOS transistor (30), the drain wiring (33a) has the same wiring width as the source wiring (32a).

Abstract translation: 为了提供具有高ESD耐受性的半导体器件，在NMOS晶体管（30）的区域中的栅极（31）和源极（32）上形成源极布线（32a）。 源极布线（32a）电连接栅极（31），源极（32）和接地端子。 漏极布线（33a）形成在NMOS晶体管（30）的区域中的漏极（33）上。 漏极布线（33a）电连接漏极（33）和用作外部连接电极的焊盘（20）。 此外，在NMOS晶体管（30）的区域中，漏极布线（33a）具有与源极布线（32a）相同的布线宽度。

公开(公告)号：US20150287714A1

公开(公告)日：2015-10-08

申请号：US14746018

申请日：2015-06-22

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Tomomitsu RISAKI

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0676 ,  H01L29/0692 ,  H01L29/8611

Abstract: A semiconductor device having a clamp diode has a breakdown voltage adjusting first conductivity type low concentration region provided on a semiconductor substrate. A second conductivity type high concentration region of circular shape is provided within the breakdown voltage adjusting first conductivity type low concentration region so as to be surrounded by the first conductivity type low concentration region but not surrounded by any other low concentration region. A first conductivity type high concentration region is provided within the first conductivity type low concentration region, without being held in contact with the second conductivity type high concentration region.

Abstract translation: 具有钳位二极管的半导体器件具有设置在半导体衬底上的击穿电压调节第一导电型低浓度区域。 在击穿电压调节第一导电型低浓度区域内设置圆形的第二导电型高浓度区域，以被第一导电型低浓度区域包围，但不被任何其它低浓度区域包围。 在第一导电型低浓度区域内设置第一导电型高浓度区域，而不与第二导电型高浓度区域保持接触。

公开(公告)号：US20130277792A1

公开(公告)日：2013-10-24

申请号：US13855781

申请日：2013-04-03

Applicant: Seiko Instruments Inc.

Inventor： Tomomitsu RISAKI

IPC: H01L27/06

CPC classification number: H01L27/0255 ,  H01L27/0676 ,  H01L29/0692 ,  H01L29/8611

Abstract: A semiconductor device having a clamp diode includes: a breakdown voltage adjusting first conductivity type low concentration region (5) provided on a semiconductor substrate (6); a second conductivity type high concentration region (1) provided within the breakdown voltage adjusting first conductivity type low concentration region (5), the second conductivity type high concentration region being circular; an element isolation insulating film (2) provided within the breakdown voltage adjusting first conductivity type low concentration region (5), the element isolation insulating film being provided in a ring shape and surrounding the second conductivity type high concentration region (1) without being held in contact therewith; and a first conductivity type high concentration region (3) provided outside the ring of the element isolation insulating film (2) within the breakdown voltage adjusting first conductivity type low concentration region (5).

Abstract translation: 具有钳位二极管的半导体器件包括：设置在半导体衬底（6）上的击穿电压调节第一导电型低浓度区（5）; 设置在所述击穿电压调整用第一导电型低浓度区域（5）内的第二导电型高浓度区域（1），所述第二导电型高浓度区域为圆形; 设置在所述击穿电压调整用第一导电型低浓度区域（5）内的元件隔离绝缘膜（2），所述元件隔离绝缘膜设置成环状并围绕所述第二导电型高浓度区域（1）而不被保持 与其接触; 以及设置在击穿电压调整用第一导电型低浓度区域（5）内的元件隔离绝缘膜（2）的环外的第一导电型高浓度区域（3）。

公开(公告)号：US20150221660A1

公开(公告)日：2015-08-06

申请号：US14602535

申请日：2015-01-22

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Tomomitsu RISAKI

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L29/7883 ,  H01L21/26586 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0653 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.

Abstract translation: 提供一种半导体器件，其防止在升压电路和存储器主体部之间的位置串联连接的MOS晶体管中的不必要的电压降，从而在低电压下操作并且提高ON / OFF比，使得 芯片尺寸缩小和记忆性能改善同时完成。 在包括存储晶体管部分和选择晶体管部分的半导体存储器件中，至少选择晶体管部分由鳍状单晶半导体薄膜形成。

公开(公告)号：US20140217510A1

公开(公告)日：2014-08-07

申请号：US14166937

申请日：2014-01-29

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takeshi KOYAMA ,  Tomomitsu RISAKI

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0277

Abstract: Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.

Abstract translation: 提供了一种使用梳状N型MOS晶体管作为ESD保护元件并能够均匀地操作整个梳状N型MOS晶体管的半导体器件。 通过调整用作ESD保护元件的N型MOS晶体管的栅电极的长度L，该长度L与设置在围绕外周的保护环上的用于固定衬底电位的接触点的距离相应， 表示为梳齿的N型MOS晶体管均匀地进入快速恢复操作，从而避免局部电流集中并获得期望的ESD容限。

公开(公告)号：US20130119472A1

公开(公告)日：2013-05-16

申请号：US13666483

申请日：2012-11-01

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Tomomitsu RISAKI ,  Shoji NAKANISHI ,  Koichi SHIMAZAKI

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L27/0259 ,  H01L27/027 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/423 ,  H01L29/735 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Abstract translation: 提供一种半导体器件，包括：在半导体衬底的表面上形成的PW层; 形成在所述半导体衬底的与所述PW层接触的表面的NW层; 形成在PW层中的半导体衬底的表面的p +基层; 形成在所述NW层的半导体衬底的表面的n +集电体层; 位于p +基极层和n +集电极层之间并形成在PW层中的半导体衬底的表面的n +发射极层; 以及形成在n +集电极层和PW层之间的与n +集电极层接触的n +层。