-
公开(公告)号：US20240006363A1
公开(公告)日：2024-01-04
申请号：US18466667
申请日：2023-09-13
发明人： Sw WANG , CH CHEW , Eiji KUROSE , How Kiat LIEW
CPC分类号： H01L24/14 , H01L24/96 , H01L23/3114 , H01L21/561 , H01L21/56 , H01L2924/0105 , H01L2924/01029
摘要： Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
-
公开(公告)号：US20190252255A1
公开(公告)日：2019-08-15
申请号：US16395822
申请日：2019-04-26
发明人： Shutesh KRISHNAN , Sw Wei WANG , CH CHEW , How Kiat LIEW , Fui Fui TAN
IPC分类号： H01L21/78 , H01L21/306 , H01L23/482
摘要： Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
-
公开(公告)号：US20190057947A1
公开(公告)日：2019-02-21
申请号：US15679666
申请日：2017-08-17
发明人： Sw WANG , CH CHEW , Eiji KUROSE , How Kiat LIEW
摘要： Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
-
公开(公告)号：US20220157756A1
公开(公告)日：2022-05-19
申请号：US17649943
申请日：2022-02-04
发明人： Sw WANG , CH CHEW , Eiji KUROSE , How Kiat LIEW
摘要： Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
-
公开(公告)号：US20190057900A1
公开(公告)日：2019-02-21
申请号：US15679664
申请日：2017-08-17
发明人： Shutesh KRISHNAN , Sw WANG , CH CHEW , How Kiat LIEW , Fui Fui TAN
IPC分类号： H01L21/78 , H01L21/306 , H01L23/482
摘要： Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
-
-
-
-
搜索结果
5 条记录 (耗时 0.013 秒)
