公开(公告)号：US20220238342A1

公开(公告)日：2022-07-28

申请号：US17659068

申请日：2022-04-13

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. SEDDON ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC分类号： H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

摘要： Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20240203744A1

公开(公告)日：2024-06-20

申请号：US18416760

申请日：2024-01-18

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. SEDDON ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC分类号： H01L21/302 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31

CPC分类号： H01L21/302 ,  H01L21/48 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3185 ,  H01L24/04 ,  H01L24/26 ,  H01L2224/94

摘要： Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

公开(公告)号：US20240006363A1

公开(公告)日：2024-01-04

申请号：US18466667

申请日：2023-09-13

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Sw WANG ,  CH CHEW ,  Eiji KUROSE ,  How Kiat LIEW

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L24/96 ,  H01L23/3114 ,  H01L21/561 ,  H01L21/56 ,  H01L2924/0105 ,  H01L2924/01029

摘要： Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

公开(公告)号：US20230118179A1

公开(公告)日：2023-04-20

申请号：US18069257

申请日：2022-12-21

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Eiji KUROSE

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/285

摘要： Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.

公开(公告)号：US20220246434A1

公开(公告)日：2022-08-04

申请号：US17660477

申请日：2022-04-25

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. SEDDON ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC分类号： H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

摘要： Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

公开(公告)号：US20210035807A1

公开(公告)日：2021-02-04

申请号：US17072521

申请日：2020-10-16

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yusheng LIN ,  Michael J. SEDDON ,  Francis J. CARNEY ,  Takashi NOMA ,  Eiji KUROSE

IPC分类号： H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

摘要： Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.

公开(公告)号：US20200279747A1

公开(公告)日：2020-09-03

申请号：US16879378

申请日：2020-05-20

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC分类号： H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

摘要： Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20200258751A1

公开(公告)日：2020-08-13

申请号：US16861810

申请日：2020-04-29

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. SEDDON ,  Francis J. CARNEY ,  Eiji KUROSE ,  Chee Hiong CHEW ,  Soon Wei WANG

IPC分类号： H01L21/302 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/31

摘要： Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

公开(公告)号：US20190057874A1

公开(公告)日：2019-02-21

申请号：US15679661

申请日：2017-08-17

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Eiji KUROSE

IPC分类号： H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00

摘要： Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.

公开(公告)号：US20220351978A1

公开(公告)日：2022-11-03

申请号：US17813351

申请日：2022-07-19

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC分类号： H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

摘要： Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.