公开(公告)号：US20240006363A1

公开(公告)日：2024-01-04

申请号：US18466667

申请日：2023-09-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Sw WANG ,  CH CHEW ,  Eiji KUROSE ,  How Kiat LIEW

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/14 ,  H01L24/96 ,  H01L23/3114 ,  H01L21/561 ,  H01L21/56 ,  H01L2924/0105 ,  H01L2924/01029

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

公开(公告)号：US20190122963A1

公开(公告)日：2019-04-25

申请号：US16031948

申请日：2018-07-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Sw WANG ,  Kai Chat TAN

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00

Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.

公开(公告)号：US20190057947A1

公开(公告)日：2019-02-21

申请号：US15679666

申请日：2017-08-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Sw WANG ,  CH CHEW ,  Eiji KUROSE ,  How Kiat LIEW

IPC: H01L23/00 ,  H01L23/31

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

公开(公告)号：US20220157756A1

公开(公告)日：2022-05-19

申请号：US17649943

申请日：2022-02-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Sw WANG ,  CH CHEW ,  Eiji KUROSE ,  How Kiat LIEW

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

公开(公告)号：US20190057900A1

公开(公告)日：2019-02-21

申请号：US15679664

申请日：2017-08-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shutesh KRISHNAN ,  Sw WANG ,  CH CHEW ,  How Kiat LIEW ,  Fui Fui TAN

IPC: H01L21/78 ,  H01L21/306 ,  H01L23/482

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.