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    THIN SEMICONDUCTOR PACKAGE AND RELATED METHODS
    2.
    发明申请
    THIN SEMICONDUCTOR PACKAGE AND RELATED METHODS 审中-公开

    公开(公告)号：US20190252255A1

    公开(公告)日：2019-08-15

    申请号：US16395822

    申请日：2019-04-26

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Shutesh KRISHNAN ,  Sw Wei WANG ,  CH CHEW ,  How Kiat LIEW ,  Fui Fui TAN

    IPC: H01L21/78 ,  H01L21/306 ,  H01L23/482

    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

    MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS
    3.
    发明申请
    MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS 审中-公开

    公开(公告)号：US20190057947A1

    公开(公告)日：2019-02-21

    申请号：US15679666

    申请日：2017-08-17

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Sw WANG ,  CH CHEW ,  Eiji KUROSE ,  How Kiat LIEW

    IPC: H01L23/00 ,  H01L23/31

    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

    CHIP-ON-LEAD SEMICONDUCTOR DEVICE PACKAGES WITH ELECTRICALLY ISOLATED SIGNAL LEADS
    5.
    发明申请
    CHIP-ON-LEAD SEMICONDUCTOR DEVICE PACKAGES WITH ELECTRICALLY ISOLATED SIGNAL LEADS 审中-公开

    公开(公告)号：US20200035586A1

    公开(公告)日：2020-01-30

    申请号：US16045275

    申请日：2018-07-25

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jin Yoong LIONG ,  Soon Wei WANG ,  How Kiat LIEW

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

    Abstract: In a general aspect, a chip-on-lead semiconductor device package can include a leadframe having a plurality of signal leads. The plurality of signal leads can include at least two signal leads each having a first face with a first surface area and, opposite the first face, a second face with a second surface area, the second faces of the at least two signal leads being exposed on a surface of the chip-on-lead device package. The plurality of signal lead can also include at least one signal lead having a first face with a third surface area and, opposite the first face of the at least one signal lead, a second face with the second surface area, the second face of the at least one signal lead being exposed on the surface of the chip-on-lead semiconductor device package.

    MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS
    6.
    发明申请
    MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS 有权

    公开(公告)号：US20220157756A1

    公开(公告)日：2022-05-19

    申请号：US17649943

    申请日：2022-02-04

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Sw WANG ,  CH CHEW ,  Eiji KUROSE ,  How Kiat LIEW

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

    THIN SEMICONDUCTOR PACKAGE AND RELATED METHODS
    7.
    发明申请
    THIN SEMICONDUCTOR PACKAGE AND RELATED METHODS 审中-公开

    公开(公告)号：US20190057900A1

    公开(公告)日：2019-02-21

    申请号：US15679664

    申请日：2017-08-17

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Shutesh KRISHNAN ,  Sw WANG ,  CH CHEW ,  How Kiat LIEW ,  Fui Fui TAN

    IPC: H01L21/78 ,  H01L21/306 ,  H01L23/482

    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

    QUAD FLAT NO LEADS PACKAGE
    9.
    发明申请
    QUAD FLAT NO LEADS PACKAGE 审中-公开

    公开(公告)号：US20180040539A1

    公开(公告)日：2018-02-08

    申请号：US15230179

    申请日：2016-08-05

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Soon Wei WANG ,  How Kiat LIEW ,  Jose Felixminia PALAGUD, JR.

    IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48

    Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

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