公开(公告)号：US20170077082A1

公开(公告)日：2017-03-16

申请号：US15251910

申请日：2016-08-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： David D. MARREIRO ,  Yupeng CHEN ,  Steven M. ETTER ,  Umesh SHARMA

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/866

CPC classification number: H01L27/0262 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/866

Abstract: An ultra-low capacitance ESD protection device with an ultra-fast response time and a low turn-on voltage, and a high holding current. The device may include: a heavily-doped p-type substrate; a lightly-doped n-type epitaxial layer with a heavily-doped n-type buried layer; and a semiconductor-controlled rectifier (SCR) structure within the epitaxial layer. The SCR structure includes, between a ground terminal and a pad terminal: a shallow P+ region within a moderately-doped n-type well to form an emitter-base junction of a trigger transistor; a shallow N+ region within a moderately-doped p-type well to form an emitter-base junction of a latching transistor, and a PN junction coupled to either of the shallow regions as a forward-biased series diode. To reduce capacitance, the n-type and p-type wells are separated by a lightly-doped portion of the epitaxial layer having a small lateral dimension for enhanced switching speed.

Abstract translation: 超低电容ESD保护器件具有超快的响应时间和低导通电压以及高保持电流。 该器件可以包括：重掺杂p型衬底; 具有重掺杂n型掩埋层的轻掺杂n型外延层; 和外延层内的半导体可控整流器（SCR）结构。 SCR结构包括在接地端子和焊盘端子之间：在中等掺杂的n型阱内的浅P +区域，以形成触发晶体管的发射极 - 基极结; 在中等掺杂的p型阱内形成浅N +区，以形成锁存晶体管的发射极 - 基极结，以及耦合到任何一个浅区的PN结作为正向偏置串联二极管。 为了减小电容，n型和p型阱由具有小横向尺寸的外延层的轻掺杂部分分开，以提高开关速度。

公开(公告)号：US20180374931A1

公开(公告)日：2018-12-27

申请号：US16103518

申请日：2018-08-14

Applicant: Semiconductor Components Industries, LLC

Inventor： Umesh SHARMA ,  Harry Yue GEE ,  Der Min LIOU ,  David D. MARREIRO ,  Sudhama C. SHASTRI

IPC: H01L29/66 ,  H01L29/861 ,  H01L23/00 ,  H01L29/866 ,  H01L27/02

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

公开(公告)号：US20160225756A1

公开(公告)日：2016-08-04

申请号：US15094853

申请日：2016-04-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： David D. MARREIRO ,  Yupeng CHEN ,  Ralph WALL ,  Umesh SHARMA ,  Harry Yue GEE

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L27/0248 ,  H01L29/7416

Abstract: In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured to enable a transistor or a transistor of an SCR responsively to an input voltage having a value that is no less than the trigger value of the ESD device.

Abstract translation: 在一个实施例中，ESD装置被配置为包括有助于形成ESD装置的触发的触发装置。 触发装置被配置为使得响应于具有不小于ESD装置的触发值的值的输入电压的SCR的晶体管或晶体管。