DIAGNOSING POWER RAIL OVER-VOLTAGE AND UNDER-VOLTAGE CONDITIONS

    公开(公告)号:US20250053218A1

    公开(公告)日:2025-02-13

    申请号:US18366895

    申请日:2023-08-08

    Abstract: Power monitors, power supply circuits, and methods for operating a power supply. The method includes determining a voltage of a power rail provided to a load device from the power supply. The method also includes detecting that the voltage of the power rail is greater than or equal to an over-voltage threshold. The method further includes incrementing an over-voltage counter when the voltage of the power rail is detected as being greater than or equal to the over-voltage threshold. The method also includes detecting that the over-voltage counter is equal to a threshold value. The method further includes generating an interrupt signal when the over-voltage counter is detected as being equal to the threshold value.

    POWER SUPPLY SYSTEM FOR DETECTING A RAIL VIOLATION IN A MULTI-RAIL SEQUENCE

    公开(公告)号:US20250004523A1

    公开(公告)日:2025-01-02

    申请号:US18344470

    申请日:2023-06-29

    Abstract: In some aspects, a power supply system includes a plurality of power supply devices configured to be connected to an integrated circuit, where a power supply device of the plurality of power supply devices includes a voltage regulator configured to generate a rail voltage, and an internal diagnostic circuit. The internal diagnostic circuit is configured to detect activation of an enable signal to activate the plurality of power supply devices according to an activation power sequence, detect a rail violation of the activation power sequence in response to a value of the rail voltage at a first time, not satisfying a first condition defined by a voltage threshold, or at a second time, not satisfying a second condition defined by the voltage threshold. In response to the rail violation being detected, the internal diagnostic circuit is configured to activate an interrupt signal.

    DEVICES, SYSTEMS AND METHODS FOR AVOIDING FAULT PROPAGATION IN SAFETY SYSTEMS

    公开(公告)号:US20210194237A1

    公开(公告)日:2021-06-24

    申请号:US16718484

    申请日:2019-12-18

    Abstract: The various embodiments of the present disclosure are directed to devices, systems and methods for mitigating fault propagation between two or more safety components. A system, for avoiding propagation of a fault between two or more safety components may include a control unit outputting an input signal, a first safety component electrically coupled to receive the input signal from the control unit; a second safety component electrically coupled to receive the input signal from the control unit; and a first isolating component electrically disposed between and further coupling the control unit with the first safety component. Each of the first safety component and the second safety component are electrically coupled to the control unit by at least a common lead. The first isolating component prevents a first IC fault arising with respect to the first safety component from propagating, via the input signal, to the second safety component.

    RESET OUTPUT WITH OPEN DRAIN CONFIGURATION FOR FUNCTIONAL SAFETY (FUSA) APPLICATIONS

    公开(公告)号:US20240377870A1

    公开(公告)日:2024-11-14

    申请号:US18315139

    申请日:2023-05-10

    Abstract: Reset output with open drain configuration for functional safety (FUSA) applications. Example embodiments include methods of operating an output of an integrated circuit (IC) including determining an error condition in the IC; generating a reset signal based on the determining the error condition in the IC; selectively conducting, by a field-effect transistor (FET), a first current between an output terminal and a ground terminal of the IC to drive the output terminal to a low voltage state, and thereby signaling the error condition in the IC; conducting a second current between a signal terminal of the IC and a gate of the FET to drive the FET to a conductive state; and selectively driving, in response to the reset signal, the FET to a non-conductive state.

    SIGNALING OPEN DRAIN READBACK FOR FUNCTIONAL SAFETY (FUSA) APPLICATIONS IN POINT OF LOAD (POL) INTEGRATED CIRCUIT

    公开(公告)号:US20240356433A1

    公开(公告)日:2024-10-24

    申请号:US18349273

    申请日:2023-07-10

    CPC classification number: H02M1/32 H02M3/155

    Abstract: Signaling open drain read back for functional safety (FUSA) applications in point of load (POL) integrated circuit. Example embodiments include methods of operating a point of load (POL) device, including: supplying power to a load via a power terminal; selectively conducting, by a field-effect transistor (FET), a current between a signal output terminal of the POL power supply device and a ground terminal of the POL power supply device to drive the signal output terminal to a low-voltage state, thereby communicating a signal; and detecting, by a monitoring circuit in the POL power supply, a status of the signal output terminal to determine whether an external device is communicating the signal on a shared communications line connected to the signal output terminal.

    BOND WIRE LOSS DETECTION AND REDUNDANCY
    8.
    发明公开

    公开(公告)号:US20230298950A1

    公开(公告)日:2023-09-21

    申请号:US17654847

    申请日:2022-03-15

    Abstract: In some aspects, the techniques described herein relate to a semiconductor device including: a package including a plurality of pins; a semiconductor die including: a first bond pad; a second bond pad; and a pass transistor having: a drain terminal electrically coupled with the first bond pad; and a source terminal electrically coupled with the second bond pad; a first bond wire extending between a pin of the plurality of pins and the first bond pad; and a second bond wire extending between the pin and the second bond pad, the pass transistor being configured to facilitate detection of at least one of: lack of electrical continuity between the pin and the first bond pad; or lack of electrical continuity between the pin and the second bond pad.

    METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR

    公开(公告)号:US20200266782A1

    公开(公告)日:2020-08-20

    申请号:US16419506

    申请日:2019-05-22

    Abstract: In an embodiment, a differential buffer may include a first input stage that compares a non-inverting portion of an input signal alternately to a non-inverting portion of an output and to an inverting portion of the output. Another embodiment of the differential buffer may also include a second input stage that compares the inverting portion of the input signal alternately to the inverting portion of the output signal and to the non-inverting portion of the output signal. Other embodiments of the differential buffer may include a feedback chopper switch that transfers the non-inverting portion of the output signal and the inverting portion of the output signal to the first input stage and to the second input stage.

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