公开(公告)号：US20200082895A1

公开(公告)日：2020-03-12

申请号：US16576836

申请日：2019-09-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G11C19/28 ,  H01L27/12 ,  G02F1/133 ,  G09G3/36 ,  G02F1/1333

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node a rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

公开(公告)号：US10424390B2

公开(公告)日：2019-09-24

申请号：US16162480

申请日：2018-10-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G09G3/36 ,  G11C19/28 ,  G02F1/1333 ,  G02F1/133 ,  H01L27/12

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

公开(公告)号：US20190147969A1

公开(公告)日：2019-05-16

申请号：US16162480

申请日：2018-10-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G11C19/28 ,  G02F1/1333 ,  G02F1/133 ,  G09G3/36 ,  H01L27/12

CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

公开(公告)号：US20180122492A1

公开(公告)日：2018-05-03

申请号：US15802524

申请日：2017-11-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G11C19/28 ,  G09G3/36 ,  H01L27/12 ,  G02F1/133 ,  G02F1/1333

CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

公开(公告)号：US20160043158A1

公开(公告)日：2016-02-11

申请号：US14920972

申请日：2015-10-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

IPC: H01L27/32 ,  H01L27/12

CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

公开(公告)号：US20150340378A1

公开(公告)日：2015-11-26

申请号：US14816124

申请日：2015-08-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: H01L27/12 ,  G02F1/133

CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

Abstract translation: 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，由TFT 105的阈值引起的电压下降，输出节点的电位上升到VDD。

公开(公告)号：US09171896B2

公开(公告)日：2015-10-27

申请号：US14614502

申请日：2015-02-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

IPC: H01L27/32 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

Abstract translation: 提供一种可以防止由于泄漏或其它原因引起的栅极电压变化并且同时可以防止开口率降低的发光器件。 电容器存储器由连接布线，绝缘膜和电容布线形成。 连接布线形成在栅电极和像素的TFT的有源层上，并与有源层连接。 绝缘膜形成在连接布线上。 电容布线形成在绝缘膜上。 这种结构使得电容器存储与TFT重叠，从而在保持开口率降低的同时增加电容器存储的容量。 因此，可以避免由于泄漏或其他原因导致的栅极电压的变化，以防止OLED的亮度变化和模拟驱动中屏幕的闪烁。

公开(公告)号：US08952385B1

公开(公告)日：2015-02-10

申请号：US14322990

申请日：2014-07-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

IPC: H01L29/04 ,  H01L27/32 ,  H01L27/12

CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

公开(公告)号：US20140159045A1

公开(公告)日：2014-06-12

申请号：US14180415

申请日：2014-02-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: H01L29/786

CPC classification number: H01L29/786 ,  H03K19/01714 ,  H03K19/01721

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node α into a floating state. When the node α is in the floating state, a potential of the node α is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD−GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract translation: 提供了一种半导体器件，其中可以通过仅使用一种导电类型的TFT构成电路并且可以正常获得输出信号的电压振幅来减小制造步骤。 电容（205）设置在连接到输出节点的TFT（203）的栅极和源极之间，并且由TFT（201）和（202）形成的电路具有使节点α成为浮置状态的功能 。 当节点α处于浮置状态时，通过使用TFT（203）通过电容（205）的栅源电容耦合，使节点α的电位高于VDD，因此具有VDD的幅度的输出信号 通常可以获得-GND，而不会由于TFT的阈值引起振幅衰减。

公开(公告)号：US20170271426A1

公开(公告)日：2017-09-21

申请号：US15614663

申请日：2017-06-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

IPC: H01L27/32 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.