公开(公告)号：US09590632B2

公开(公告)日：2017-03-07

申请号：US14702834

申请日：2015-05-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC: H03K19/096 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H03K19/017

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

Abstract translation: 提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。 当输入时钟信号CK1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置为低电平。 然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起来。 TFT（102）因此被导通。 然后，CK1变为低电平，并且每个TFT（101,103）被关断。 同时，CK3变为高电平，信号输出部分的电位增加。 同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。 当SP变低时 CK3变低 并且CK1变为高电平时，信号输出部（Out）的电位再次变为低电平。

公开(公告)号：US09812218B2

公开(公告)日：2017-11-07

申请号：US15343373

申请日：2016-11-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G11C19/28 ,  H01L27/12 ,  G02F1/133 ,  G09G3/36 ,  G02F1/1333

CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

公开(公告)号：US20170076820A1

公开(公告)日：2017-03-16

申请号：US15343373

申请日：2016-11-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G11C19/28 ,  G09G3/36 ,  H01L27/12

CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

Abstract translation: 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，由TFT 105的阈值引起的电压下降，输出节点的电位上升到VDD。

公开(公告)号：US09496291B2

公开(公告)日：2016-11-15

申请号：US14816124

申请日：2015-08-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: H01L27/12 ,  G02F1/133 ,  G09G3/36 ,  G11C19/28 ,  G02F1/1333

CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

公开(公告)号：US20140327008A1

公开(公告)日：2014-11-06

申请号：US14332468

申请日：2014-07-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: H01L27/12 ,  G02F1/1333

CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

Abstract translation: 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，由TFT 105的阈值引起的电压下降，输出节点的电位上升到VDD。

公开(公告)号：US10916319B2

公开(公告)日：2021-02-09

申请号：US16576836

申请日：2019-09-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G09G3/36 ,  G11C19/28 ,  H01L27/12 ,  G02F1/133 ,  G02F1/1333

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node a rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

公开(公告)号：US20170243554A1

公开(公告)日：2017-08-24

申请号：US15447232

申请日：2017-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

公开(公告)号：US09136385B2

公开(公告)日：2015-09-15

申请号：US14180415

申请日：2014-02-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: H01L29/786 ,  H03K19/017

CPC classification number: H01L29/786 ,  H03K19/01714 ,  H03K19/01721

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node α into a floating state. When the node α is in the floating state, a potential of the node α is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD−GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract translation: 提供了一种半导体器件，其中可以通过仅使用一种导电类型的TFT构成电路并且可以正常获得输出信号的电压振幅来减小制造步骤。 电容（205）设置在连接到输出节点的TFT（203）的栅极和源极之间，并且由TFT（201）和（202）形成的电路具有使节点α成为浮置状态的功能 。 当节点α处于浮置状态时，通过使用TFT（203）通过电容（205）的栅源电容耦合，使节点α的电位高于VDD，因此具有VDD的幅度的输出信号 通常可以获得-GND，而不会由于TFT的阈值引起振幅衰减。

公开(公告)号：US20130251091A1

公开(公告)日：2013-09-26

申请号：US13760147

申请日：2013-02-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

Abstract: A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

Abstract translation: 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，后级的输出被输入到TFT103，使TFT103导通，同时电位 的TFT102和106的节点α的下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。

公开(公告)号：US20200082895A1

公开(公告)日：2020-03-12

申请号：US16576836

申请日：2019-09-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC: G11C19/28 ,  H01L27/12 ,  G02F1/133 ,  G09G3/36 ,  G02F1/1333

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node a rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.