Abstract:
A pixel structure is disclosed. The pixel structure includes a substrate, a plurality of scan lines, and a plurality of data lines crossing the scan lines to form pixel unit areas, where the data lines are insulated from the scan lines. The pixel structure also includes a plurality of first electrodes formed in the pixel unit areas, a plurality of second electrodes insulated from the first electrodes and located closer to the substrate than the first electrodes, and a plurality of signal lines located in a same layer as topmost electrodes farthest from the substrate, where the signal lines are arranged to be insulated from the topmost electrodes.
Abstract:
Provided are an array substrate, a display panel, and a display device. The array substrate includes a base substrate, scanning lines extending along first direction and data lines extending along second direction disposed on base substrate, pixel units arranged in an array along first direction and second direction; touch electrodes and touch traces disposed on base substrate, and a first insulating layer disposed between the touch traces and the touch electrodes in a direction perpendicular to base substrate. Each touch trace is connected to the touch electrodes via a first through hole in the first insulating layer. Two scanning lines are disposed between two adjacent pixel units in the second direction, and each scanning line controls its adjacent pixel unit. An orthographic projection of the first through hole on the base substrate is located between the two scanning lines and does not overlap with them.
Abstract:
A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register.
Abstract:
Embodiments of the invention provide a gate drive apparatus and a display apparatus. With the gate drive apparatus, a clock signal is used in place of a forward scan signal and/or a clock signal is used in place of a backward scan signal and/or a reset signal and a first initial trigger signal (or a second initial trigger signal) are used in place of a low level signal and/or the same signal is used as a first initial trigger signal and a second initial trigger signal to thereby reduce the number of transmission lines for signals driving the gate drive apparatus.
Abstract:
An array substrate, a display panel, and a display device are provided. The array substrate includes a substrate, and a plurality of scanning lines and a plurality of data lines disposed on the substrate. The plurality of scanning lines and the plurality of data lines are insulated and intersected to define a plurality of pixel units. Each pixel unit includes a thin film transistor and a pixel electrode, a gate electrode of the thin film transistor is electrically connected to a scanning line, a source electrode is electrically connected to a data line, and a drain electrode is electrically connected to the pixel electrode. An active layer of the thin film transistor includes at least one channel region including first sub-channel region and at least one second sub-channel region. A first width of the first sub-channel region is smaller than a second width of the second sub-channel region.