公开(公告)号：US20040228180A1

公开(公告)日：2004-11-18

申请号：US10843149

申请日：2004-05-10

申请人： SHARP KABUSHIKI KAISHA

发明人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C016/12

CPC分类号： G11C16/3468

摘要： The present invention provides a method of programming, into a computer, a memory array having a plurality of memory cells, including a verification step 1 of verifying whether a memory cell has been already programmed or it has not been programmed yet per memory cell to be programmed, a flagging step 2 of flagging the memory cell in the case where it is verified that the memory cell has not been programmed yet in the several verifying steps, to which the memory cell is subjected thereafter, even if it is verified that the memory cell has been already programmed, a first application step 3 of applying a programming pulse having a programming level to the not-programmed memory cell without any flag, a repeat step 4 of repeating the verification step 1, the flagging step 2 and the first application step 3 until it is verified that all of the memory cells have been already programmed at least once, and a second application step 5 of applying a boost pulse having a boost programming level lower than that of the programming level to the memory cell with the flag.

摘要翻译： 本发明提供了一种对计算机编程具有多个存储单元的存储器阵列的方法，所述存储器阵列包括验证步骤1，该验证步骤1验证存储器单元是否已被编程，或者每个存储器单元尚未被编程 在存储单元受此之后验证存储单元尚未被编程的几个验证步骤的情况下，标记存储单元的标记步骤2，即使确认存储器 单元已经被编程，第一应用步骤3，将没有任何标志的具有编程级别的编程脉冲施加到未编程的存储器单元;重复步骤4，重复验证步骤1，标记步骤2和第一应用 步骤3，直到验证所有存储器单元已经被编程至少一次，以及施加具有升压编程电平的升压脉冲的第二应用步骤5 比编程级别低到具有标志的存储单元。

公开(公告)号：US20040222456A1

公开(公告)日：2004-11-11

申请号：US10840173

申请日：2004-05-05

申请人： SHARP KABUSHIKI KAISHA

发明人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L029/788

CPC分类号： H01L29/66833 ,  G11C16/10 ,  G11C16/30 ,  H01L21/28282 ,  H01L29/7923

摘要： A computer system comprising: (A) a CPU; (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors; (ii) a charge pump; (iii) a plurality of switching circuits; and (iv) logic circuitry; and (C) a system bus, wherein each of the side-wall memory transistors comprises: a gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional units formed on the both sides of the gate electrode and having a function of retaining charges.

摘要翻译： 一种计算机系统，包括：（A）CPU; （B）存储装置，包括：（i）包括多个侧壁存储晶体管的侧壁存储器阵列; （ii）电荷泵; （iii）多个开关电路; 和（iv）逻辑电路; 和（C）系统总线，其中每个侧壁存储晶体管包括：形成在半导体层上的栅电极，其上形成有在半导体层上的栅极绝缘膜; 形成在栅电极下方的沟道区; 一对扩散区，形成在沟道区的两侧，具有与沟道区相反的导电类型; 以及形成在栅电极的两侧并具有保持电荷的功能的一对记忆功能单元。

公开(公告)号：US20040262666A1

公开(公告)日：2004-12-30

申请号：US10850806

申请日：2004-05-20

申请人： SHARP KABUSHIKI KAISHA

发明人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L029/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation, with respect to one of the memory elements, to the memory element via a bit line connected thereto, and thereafter, applying a second voltage for verifying whether or not the write or erase operation has been performed, to the memory element via the bit line, and a reset portion for grounding the bit line connected to the memory element after the write state machine has applied the first voltage and before the write state machine has applied the second voltage. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

摘要翻译： 提供一种半导体存储装置，其包括存储器阵列，该存储器阵列包括存储器元件，用于将相对于其中一个存储器元件执行写或擦除操作的第一电压经由位线施加到存储元件的写状态机 之后，经由位线向存储元件施加用于验证是否已经执行了写入或擦除操作的第二电压，以及用于在写入之后将连接到存储元件的位线接地的复位部分 状态机已经施加了第一电压，并且在写状态机施加第二电压之前。 每个存储元件包括栅电极，沟道区，扩散区和设置在栅电极的相对侧上并具有保持电荷的功能的存储功能部。

公开(公告)号：US20040262650A1

公开(公告)日：2004-12-30

申请号：US10899183

申请日：2004-07-27

申请人： Sharp Kabushiki Kaisha

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L031/0328 ,  H01L021/336 ,  H01L029/76

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-Anull. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个 具有用于接触接触导体的第二表面。 第二面相对于第一面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US20030107103A1

公开(公告)日：2003-06-12

申请号：US10322663

申请日：2002-12-19

申请人： Sharp Kabushiki Kaisha

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L029/00

CPC分类号： H01L21/76229 ,  H01L21/823807 ,  H01L29/783

摘要： A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, Bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

公开(公告)号：US20040223372A1

公开(公告)日：2004-11-11

申请号：US10841688

申请日：2004-05-06

申请人： SHARP KABUSHIKI KAISHA

发明人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C016/34

CPC分类号： H01L29/7923 ,  G11C16/3454 ,  H01L21/28282

摘要： A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell. It is thereby possible to improve the speed of writing and erasing processes on a nonvolatile memory cell of the present invention and to improve reliability.

摘要翻译： 本发明的半导体存储器件包括电可编程和可擦除的非易失性存储器件，其使用需要第一电位读取数据的多个存储器单元和用于数据编程的第二电位，第二电位高于第一电位， 锁存电路，用于接收数据和临时存储数据;脉冲发生器，其生成用于将数据编程到存储器单元中并被耦合以便接收第二电位的脉冲;比较器，用于将锁存电路中的数据与 存储单元和控制器，用于控制脉冲发生器重复产生脉冲，直到锁存电路中的数据与存储单元中的数据匹配，该控制器耦合到比较器和脉冲发生器。 控制器控制，使脉冲重复生成，直到数据被编程到存储单元中。 由此，能够提高本发明的非易失性存储单元的写入和擦除处理速度，提高可靠性。

公开(公告)号：US20040264252A1

公开(公告)日：2004-12-30

申请号：US10850212

申请日：2004-05-19

申请人： Sharp Kabushiki Kaisha

发明人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C011/34

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a memory cell array in which plural memory cells are arranged, a memory operation circuit, connected to the memory cell array, for executing a memory operation on the memory cell array, and a command controller, connected to the memory operation circuit, for receiving a command from the outside and generating a predetermined control signal to the memory operation circuit on the basis of the received command to control execution of the memory operation by the memory operation circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

公开(公告)号：US20040233717A1

公开(公告)日：2004-11-25

申请号：US10846875

申请日：2004-05-13

申请人： SHARP KABUSHIKI KAISHA

发明人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C016/10

CPC分类号： G11C16/102

摘要： A semiconductor memory device of the present invention includes a first memory array, a first address register for storing therein a first address of the first memory array, a second memory array, a second address register for storing therein a second address of the second memory array, a multiplexer connected to the first memory array and the second memory array and to a memory output unit for selectively outputting the first memory array or the second memory array, and an array selection circuit for selecting the first memory array for re-programming in accordance with an input address and selecting the second memory array for a reading operation. The array selection circuit sends the first address to the, first address register, sends the second address to the second address register, and further, controls the multiplexer, so as to allow the second memory array to be connected to the memory output unit during re-programming of the first memory array. Each of the first memory array and the second memory array includes a plurality of nonvolatile memory cells. It is therefore possible to improve processing speed by enabling data to be read in a re-programming process on the semiconductor memory device.

摘要翻译： 本发明的半导体存储器件包括第一存储器阵列，用于在其中存储第一存储器阵列的第一地址的第一地址寄存器，第二存储器阵列，第二地址寄存器，用于在其中存储第二存储器阵列的第二地址 连接到第一存储器阵列和第二存储器阵列的多路复用器以及用于选择性地输出第一存储器阵列或第二存储器阵列的存储器输出单元，以及用于选择第一存储器阵列以进行重新编程的阵列选择电路 具有输入地址并选择用于读取操作的第二存储器阵列。 阵列选择电路将第一地址发送给第一地址寄存器，将第二地址发送到第二地址寄存器，并且进一步控制多路复用器，以便允许第二存储器阵列在重新连接到存储器输出单元 - 编程第一个存储器阵列。 第一存储器阵列和第二存储器阵列中的每一个包括多个非易失性存储器单元。 因此，可以通过在半导体存储器件的重新编程处理中读取数据来提高处理速度。

公开(公告)号：US20040228178A1

公开(公告)日：2004-11-18

申请号：US10843079

申请日：2004-05-10

申请人： SHARP KABUSHIKI KAISHA

发明人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C016/30

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/30 ,  G11C16/3468 ,  G11C16/3477 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device has a malfunction prevention device and a nonvolatile memory. The nonvolatile memory is a memory cell including: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed below the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having a function of retaining charges.

摘要翻译： 半导体存储器件具有故障防止装置和非易失性存储器。 非易失性存储器是包括：通过栅极绝缘膜形成在半导体层上的栅电极的存储单元; 设置在所述栅电极下方的沟道区; 扩散区域设置在沟道区域的两侧并且具有与沟道区域的导电类型相反的导电类型; 以及形成在栅电极的两侧并具有保持电荷的功能的记忆功能单元。

公开(公告)号：US20040222452A1

公开(公告)日：2004-11-11

申请号：US10836907

申请日：2004-04-30

申请人： SHARP KABUSHIKI KAISHA

发明人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata ,  Kohji Hamaguchi

IPC分类号： H01L027/108

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  G11C16/0491 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

摘要： A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges. The method includes the steps of: selecting a row line connected to the gate electrode of a memory cell to be selected; grounding a first column line connected to the source of the memory cell to be selected; and applying a first potential to a second column line and a second potential to a third column line at the same time.

摘要翻译： 用于驱动半导体存储器件的方法包括具有以行和列排列的多个存储单元的存储器阵列。 每个存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，作为扩散区域的源极和漏极，设置在沟道区域的两侧并且具有与 沟道区域和存储功能单元形成在栅电极的两侧并且具有保持电荷的功能。 该方法包括以下步骤：选择连接到要选择的存储单元的栅电极的行线; 将连接到要选择的存储单元的源的第一列线接地; 并且同时将第一电位施加到第二列线和第二电位到第三列线。