A LIFI DEVICE
    2.
    发明申请

    公开(公告)号:US20220397243A1

    公开(公告)日:2022-12-15

    申请号:US17773762

    申请日:2020-11-03

    IPC分类号: F21K9/232 F21K9/238

    摘要: The one or more LED filaments (110) are arranged to form an inner space. At least one of the one or more LED filaments (110) is arranged as a LiFi transmitter. The LiFi device (100) further comprises a light sensor (120) arranged within the inner space. The light sensor (120) is arranged as a LiFi receiver. The LiFi device further comprises an envelope arranged to envelope the one or more LED filaments (110) and the light sensor (120). The one or more LED filaments (110) are further arranged such that the LED filament light is directed towards the envelope.

    A LIGHTING UNIT AND DRIVING METHOD

    公开(公告)号:US20210007193A1

    公开(公告)日:2021-01-07

    申请号:US16982556

    申请日:2019-03-25

    摘要: A lighting unit which includes a driver, a light source and a buffer capacitor of an auxiliary circuit (such as an independent active electronic circuit). The charging current allowed to flow to the buffer capacitor is controlled based on sensed currents flowing to the light source thereby to control the charging current of the buffer capacitor. In this way, large inrush currents caused by the use of a large buffer capacitor at the output of the driver can be avoided and the triggering of a fault detection mode within the driver can be prevented. Furthermore this circuit ensures that the driver is operated within the specification limits during start-up.

    AN APD BIAS CIRCUIT WITH DUAL ANALOG FEEDBACK LOOP CONTROL

    公开(公告)号:US20240271998A1

    公开(公告)日:2024-08-15

    申请号:US18568420

    申请日:2022-06-03

    IPC分类号: G01J1/44 G01K7/22

    摘要: A bias circuit (100) of an avalanche photodiode, APD, comprising: a voltage conversion module (110) connected to the APD, wherein the voltage conversion module (110) is configured to convert an input supply voltage (Vin) to a bias voltage for the APD; an error amplifier (120) connected to the voltage conversion module (110) for implementing a feedback control; a voltage feedback loop (130) configured to provide the error amplifier (120) a first analog signal related to the bias voltage; and a current feedback loop (140) configured to provide the error amplifier (120) a second analog signal related to the APD current; wherein the error amplifier (120) is configured to control the voltage conversion module (110) based on the first and the second analog signals.

    TRIGGER-BASED OPTICAL WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20230224038A1

    公开(公告)日:2023-07-13

    申请号:US18014681

    申请日:2021-06-23

    IPC分类号: H04B10/116

    CPC分类号: H04B10/116

    摘要: High-speed optical communication is very attractive to satisfy high throughput applications. In the meanwhile, it is also desirable to reduce the energy waste resulted from an idle state of the optical transceivers of the communication system. The present invention discloses that both the access point (1200) and the end point device (1100) can operate in at least two different operation states, a normal operation state and a low power state. The low power state is a default state, and the normal operation state is enabled only when a valid trigger is detected. To establish a high-speed optical link (60), the end point device (1100) first sends an optical trigger signal (50) to the access point (1200) in the low power state. The access pint (1200) switches to the normal operation state only when a valid trigger signal is identified after detecting the optical trigger signal (50).

    LOW POWER CONVERTER FOR COMPENSATING MAINS VOLTAGE VARIATION

    公开(公告)号:US20240306275A1

    公开(公告)日:2024-09-12

    申请号:US18280734

    申请日:2022-02-28

    摘要: A power converter for compensating voltage variation in a circuit, the circuit comprising: a power stage arranged for receiving a mains input and for converting the mains input into a direct current, DC, output for driving a load; and a first buffer capacitor connected in a parallel branch with the load; wherein the power converter comprises an output capacitor connected in series with the first buffer capacitor, wherein the output capacitor is arranged for connecting in series with the first buffer capacitor in said parallel branch with the load; wherein the power converter comprises a second buffer capacitor arranged for connecting in series with the first buffer capacitor; and wherein the power converter is configured to charge the output capacitor from the second buffer capacitor, when the DC output is below a predetermined threshold.