公开(公告)号：US20140308786A1

公开(公告)日：2014-10-16

申请号：US14318077

申请日：2014-06-27

Applicant: SK hynix Inc.

Inventor： Jang Uk LEE ,  Sung Cheoul KIM ,  Kang Sik CHOI ,  Suk Ki KIM

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

Abstract translation: 半导体存储器件包括半导体衬底，包括多个单元有源区并且设置在半导体衬底之上并与其隔开的有源区，形成在单位有效区的顶表面和侧面上的一对字线，虚拟字 设置在单元有源区的接触处并形成在单元有源区的顶表面和侧面上的线，在该对字线之间的单元有源区中的源极区，并且电连接到半导体衬底，形成在该半导体衬底中的漏极区 在一对字线和伪字线之间的单位有效区域，以及形成在漏极区域上并电连接到漏极区域的第一存储层。

公开(公告)号：US20130157434A1

公开(公告)日：2013-06-20

申请号：US13731522

申请日：2012-12-31

Applicant: SK Hynix Inc.

Inventor： Jang Uk LEE

IPC: H01L45/00

CPC classification number: H01L45/16 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

Abstract: A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract translation: 提供一种相变存储装置，其包括具有形成在半导体衬底的有源区上的沟槽的棒状的第一电极，形成在沟槽的底部的第二电极和形成在第二沟道的底部的底部电极触点 电极。

公开(公告)号：US20140248765A1

公开(公告)日：2014-09-04

申请号：US14274428

申请日：2014-05-09

Applicant: SK hynix Inc.

Inventor： Jang Uk LEE

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

Abstract translation: 提供一种具有形成在互连上并能够降低互连电阻的单元图形的半导体存储器件及其制造方法。 半导体器件包括其中限定了单元区域，核心区域和外围区域并形成底部结构的半导体基板，形成在半导体基板的整个结构上的导电线，形成在该半导体基板上的存储单元图案 电池区域中的导线，以及形成在芯区域和外围区域中的导电线中的任一个上的虚设导电图案。

公开(公告)号：US20140167149A1

公开(公告)日：2014-06-19

申请号：US13845857

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Jang Uk LEE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/2815 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7827

Abstract: A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure.

Abstract translation: 半导体器件包括形成在从半导体衬底延伸的结构的侧壁上的栅电极。 结构区域从结构的顶部形成为距离结构的顶部的第一深度并且形成为与栅电极重叠。 在结构的外壁和栅电极之间形成保护层至小于距结构顶部的第一深度的第二深度。

公开(公告)号：US20150187911A1

公开(公告)日：2015-07-02

申请号：US14643695

申请日：2015-03-10

Applicant: SK hynix Inc.

Inventor： Jang Uk LEE

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/2815 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7827

Abstract: A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure.

Abstract translation: 半导体器件包括形成在从半导体衬底延伸的结构的侧壁上的栅电极。 结构区域从结构的顶部形成为距离结构的顶部的第一深度并且形成为与栅电极重叠。 在结构的外壁和栅电极之间形成保护层至小于距结构顶部的第一深度的第二深度。