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    MEMORY CELL ARRAY AND VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME
    2.
    发明申请
    MEMORY CELL ARRAY AND VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME 有权
    存储单元阵列和包括其的可变电阻存储器件

    公开(公告)号：US20140319451A1

    公开(公告)日：2014-10-30

    申请号：US14328382

    申请日：2014-07-10

    Applicant: SK hynix Inc.

    Inventor： Sung Cheoul KIM ,  Kang Sik CHOI

    IPC: H01L27/24

    CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/126

    Abstract: A memory cell array includes a semiconductor substrate, a first word line formed on the semiconductor substrate, a second word line formed on the semiconductor substrate and extending substantially parallel to the first word line, a first inter-pattern insulating layer interposed between the first and second word lines, first active pillars formed within the first word line and arranged along the first word line at a first interval, and second active pillars formed within the second word lines, and arranged along the second word line to face the first active pillars, respectively, with the first inter-pattern insulating layer interposed therebetween.

    Abstract translation: 存储单元阵列包括半导体衬底，形成在半导体衬底上的第一字线，形成在半导体衬底上并基本上平行于第一字线延伸的第二字线，插入在第一和第二字线之间的第一图案间绝缘层， 第二字线，形成在第一字线内并以第一间隔布置在第一字线上的第一活动柱和形成在第二字线内的第二活动柱，并且沿第二字线布置以面对第一活动柱， 分别具有介于其间的第一图案间绝缘层。

    DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE
    3.
    发明申请
    DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE 审中-公开
    具有组合记忆块和堆叠包的数据处理系统

    公开(公告)号：US20160210235A1

    公开(公告)日：2016-07-21

    申请号：US15063012

    申请日：2016-03-07

    Applicant: SK hynix Inc.

    Inventor： Hae Chan PARK ,  Sung Cheoul KIM ,  Tae Ho KIM

    IPC: G06F12/08 ,  G06F13/40

    CPC classification number: G06F13/4022 ,  G06F2212/451 ,  G11C11/005 ,  G11C11/5607 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/06 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2213/71 ,  G11C2213/79 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.

    Abstract translation: 数据处理系统包括中央处理单元（CPU），配置成与CPU接口的控制块，配置为与控制块接口并被布置为与CPU间隔第一距离的高速缓存存储器，以及组合存储器 其被配置为与所述控制块接口，被布置成与所述CPU间隔大于所述第一距离的第二距离，并且由工作存储器和存储存储器构成。 组合存储块由多个堆叠存储器层构成，每个堆叠存储层由多个可变电阻存储单元构成。 工作存储器被分配给在多个存储器层中选择的一个存储器层。 存储存储器被分配给多个存储器层中的剩余存储器层。

    HIGH-INTEGRATION SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    HIGH-INTEGRATION SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    高集成半导体存储器件及其制造方法

    公开(公告)号：US20140308786A1

    公开(公告)日：2014-10-16

    申请号：US14318077

    申请日：2014-06-27

    Applicant: SK hynix Inc.

    Inventor： Jang Uk LEE ,  Sung Cheoul KIM ,  Kang Sik CHOI ,  Suk Ki KIM

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

    Abstract translation: 半导体存储器件包括半导体衬底，包括多个单元有源区并且设置在半导体衬底之上并与其隔开的有源区，形成在单位有效区的顶表面和侧面上的一对字线，虚拟字 设置在单元有源区的接触处并形成在单元有源区的顶表面和侧面上的线，在该对字线之间的单元有源区中的源极区，并且电连接到半导体衬底，形成在该半导体衬底中的漏极区 在一对字线和伪字线之间的单位有效区域，以及形成在漏极区域上并电连接到漏极区域的第一存储层。

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