公开(公告)号：US20240379621A1

公开(公告)日：2024-11-14

申请号：US18483489

申请日：2023-10-09

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

Abstract: In an embodiment of the disclosed technology, a semiconductor system may include a substrate; a first memory chip supported by the substrate, wherein the first memory chip includes a first main pad structured to be electrically connected to an interconnection structure disposed outside the first memory chip and a first sub pad electrically connected to the first main pad; and one or more second memory chips supported by the substrate, wherein each of the one or more second memory chips includes a second main pad structured to be electrically connected to an interconnection structure disposed outside the first memory chip and a second sub pad electrically connected to the second main pad, and the second main pad or the second sub pad included in one second memory chip of the one or more second memory chips is electrically connected to the first sub pad by a first internal interconnection structure.

公开(公告)号：US20240134747A1

公开(公告)日：2024-04-25

申请号：US18485329

申请日：2023-10-11

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/108 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688

Abstract: A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

公开(公告)号：US20230136664A1

公开(公告)日：2023-05-04

申请号：US17979189

申请日：2022-11-02

Applicant: SK hynix Inc.

Inventor： Ie Ryung PARK ,  Dong Sop LEE

IPC: G06F3/06

Abstract: A storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. The memory controller may be further configured to store the write data in the memory device in response to the write command. The memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.

公开(公告)号：US20230073148A1

公开(公告)日：2023-03-09

申请号：US17903557

申请日：2022-09-06

Applicant: SK hynix Inc.

Inventor： Ie Ryung PARK ,  Dong Sop LEE ,  Youn Won PARK

IPC: G06F3/06 ,  G06F11/10

Abstract: A storage device includes a memory device including one or more memory blocks including first sub-areas and second sub-areas configured to store higher level data than the first sub-areas, and a controller configured to use the first sub-areas before the second sub-areas in order to store data in the memory device.

公开(公告)号：US20220148629A1

公开(公告)日：2022-05-12

申请号：US17307362

申请日：2021-05-04

Applicant: SK hynix Inc.

Inventor： Ie Ryung PARK ,  Hyun Sub KIM ,  Dong Sop LEE

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14

Abstract: The present technology relates to an electronic device. More specifically, the present technology relates to a memory device, a storage device, and a method of operating a memory controller. According to an embodiment, a memory device that outputs read data in response to a read enable signal provided from a memory controller includes a plurality of memory cells configured to store data, a plurality of page buffers configured to sense the data stored in the plurality of memory cells through a plurality of bit lines, and a data output controller configured to select a target page buffer to output data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller and control the selected target page buffer to output data stored in the selected target page buffer according to the read enable signal, while the read enable signal is input.

公开(公告)号：US20190188331A1

公开(公告)日：2019-06-20

申请号：US16031672

申请日：2018-07-10

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE

IPC: G06F17/30 ,  G06F12/1018 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04

Abstract: A memory system includes a memory device configured to store data, and a memory controller configured to perform communication between a host and the memory device and to control the memory device such that, during an operation of programming sequential data, a hash value is generated from logical block addresses of a memory area, to which the sequential data is to be written, and the hash value is stored and such that, during an operation of reading the sequential data, the sequential data is read from the memory area based on the hash value.

公开(公告)号：US20240339171A1

公开(公告)日：2024-10-10

申请号：US18490685

申请日：2023-10-19

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE ,  Tae Ho LIM

IPC: G11C29/52 ,  H03M13/00 ,  H03M13/11

CPC classification number: G11C29/52 ,  H03M13/11 ,  H03M13/611

Abstract: A phase-change memory controller controls a phase-change memory device. The phase-change memory controller includes a write control circuit configured to receive first write data of “N” bits (where “N” is a natural number greater than 2) to be written to the phase-change memory device to generate second write data composed of compressed data compressed with “M” bits (where “N” is a natural number smaller than “N”) and “0” padding data in which the rest “N-M” bits are filled with “0”.

公开(公告)号：US20240273041A1

公开(公告)日：2024-08-15

申请号：US18643881

申请日：2024-04-23

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F2213/16

Abstract: A device for implementing a storage architecture includes a front-end chip configured to perform first interfacing with a first device, a plurality of back-end chips configured to perform second interfacing with second devices, and an input/output chip disposed to be separated from the front-end chip and the plurality of back-end chips and configured to perform a communication between the second devices and the plurality of back-end chips.

公开(公告)号：US20240242742A1

公开(公告)日：2024-07-18

申请号：US18204806

申请日：2023-06-01

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE

IPC: G11C5/14

CPC classification number: G11C5/147

Abstract: Data storage systems and semiconductor devices are disclosed. In an embodiment, a storage system includes a circuit board, a semiconductor device coupled to the circuit board and including at least one memory and a controller, wherein the controller is in communication with the at least one memory and configured to control the at least one memory, and a voltage level regulator coupled to the circuit board and including at least one switching element and located outside the at least one memory and the controller in the semiconductor device, the voltage level regulator configured to output, to at least one of the at least one memory or the controller, a driving voltage obtained by adjusting a level of at least one external voltage received from a device outside the semiconductor device.

公开(公告)号：US20240232015A9

公开(公告)日：2024-07-11

申请号：US18485329

申请日：2023-10-12

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/108 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688

Abstract: A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.