公开(公告)号：US20240302993A1

公开(公告)日：2024-09-12

申请号：US18457179

申请日：2023-08-28

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE ,  Ie Ryung PARK ,  Tae Ho LIM

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device including a plurality of zones, a memory device including a plurality of zones; a buffer memory device including a plurality of slots; and a memory controller including a plurality of zone buffers respectively corresponding to the plurality of zones. The memory controller may store write data in one or more of the plurality of slots, store map data corresponding to the write data in a zone buffer that corresponds to a zone in which the write data is to be stored, and then store the write data, which is stored in the one or more slots, in the zone corresponding to the zone buffer based on the map data stored in the zone buffer.

公开(公告)号：US20240289054A1

公开(公告)日：2024-08-29

申请号：US18447981

申请日：2023-08-10

Applicant: SK hynix Inc.

Inventor： Ie Ryung PARK ,  Joo Hyung KIM ,  Dong Sop LEE ,  Tae Ho LIM

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: Provided is a method by which a second chip obtains a control code such as firmware in a memory controller having a chiplet-based structure. The memory controller includes a first chip configured to perform a first operation, a plurality of second chips configured to perform a second operation, a plurality of data links configured to connect the first chip and each of the plurality of second chips on a one-to-one basis and used for data transmission between the first chip and each of the plurality of second chips during normal operation after booting, a control link connected to the first chip and all the plurality of second chips and used to transmit a control code for performing the second operation of the plurality of second chips, and a memory connected to the first chip to store the control code of the plurality of second chips.

公开(公告)号：US20240069796A1

公开(公告)日：2024-02-29

申请号：US18151429

申请日：2023-01-07

Applicant: SK hynix Inc.

Inventor： Tae Ho LIM ,  Ie Ryung PARK ,  Dong Sop LEE ,  Youn Won PARK ,  Jae Min JANG

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

公开(公告)号：US20240339171A1

公开(公告)日：2024-10-10

申请号：US18490685

申请日：2023-10-19

Applicant: SK hynix Inc.

Inventor： Dong Sop LEE ,  Tae Ho LIM

IPC: G11C29/52 ,  H03M13/00 ,  H03M13/11

CPC classification number: G11C29/52 ,  H03M13/11 ,  H03M13/611

Abstract: A phase-change memory controller controls a phase-change memory device. The phase-change memory controller includes a write control circuit configured to receive first write data of “N” bits (where “N” is a natural number greater than 2) to be written to the phase-change memory device to generate second write data composed of compressed data compressed with “M” bits (where “N” is a natural number smaller than “N”) and “0” padding data in which the rest “N-M” bits are filled with “0”.

公开(公告)号：US20240371422A1

公开(公告)日：2024-11-07

申请号：US18773410

申请日：2024-07-15

Applicant: SK hynix Inc.

Inventor： Tae Ho LIM ,  Seung Jin PARK ,  Ie Ryung PARK ,  Dong Sop LEE

IPC: G11C7/22 ,  G11C7/10

Abstract: A data receiving circuit includes a forwarded fast clock domain configured to output data transmitted from a data transmitting circuit in synchronization with a forwarded fast clock signal, and a local clock domain configured to generate a synchronized fetch enable signal in synchronization with a local fast clock signal and output the data transmitted from the forwarded fast clock domain in synchronization with a local slow clock.

公开(公告)号：US20240331790A1

公开(公告)日：2024-10-03

申请号：US18482464

申请日：2023-10-06

Applicant: SK hynix Inc.

Inventor： Tae Ho LIM ,  Ie Ryung PARK ,  Dong Sop LEE

IPC: G11C29/18 ,  G11C29/00 ,  G11C29/02

CPC classification number: G11C29/18 ,  G11C29/006 ,  G11C29/021

Abstract: Provided herein may be a storage device for supporting dynamic allocation of memory and a method of operating the same. The storage device may include a plurality of memory dies, a state detector configured to detect respective memory states of the plurality of memory dies, a memory information storage configured to store defect information that is information about memory dies in which defects have occurred among the plurality of memory dies, and a memory controller configured to, in response to a memory die allocation request for performing an operation corresponding to an externally provided operation request, determine allocation of a memory die based on a result of comparison between each detected memory state and the defect information.