公开(公告)号：US11137939B2

公开(公告)日：2021-10-05

申请号：US16253023

申请日：2019-01-21

申请人： SK hynix Inc.

发明人： Young-Jun Yoon ,  Hyun-Seung Kim

IPC分类号： G06F3/06

摘要： A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

公开(公告)号：US10008252B2

公开(公告)日：2018-06-26

申请号：US15477619

申请日：2017-04-03

申请人： SK hynix Inc.

发明人： Sang-Ah Hyun ,  Tae-Jin Kang ,  Hyun-Seung Kim ,  Nam-Kyu Jang ,  Won-Seok Choi ,  Won-Kyung Chung ,  Seung-Hun Lee

IPC分类号： G11C7/00 ,  G11C11/35 ,  G11C7/22 ,  G11C11/404 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4093

CPC分类号： G11C11/35 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22 ,  G11C11/404 ,  G11C11/40607 ,  G11C11/4082 ,  G11C11/4093 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/105

摘要： A semiconductor system may include: an external channel including a CA (Command/Address) channel, and first and second data channels; and first and second semiconductor chips, which are coupled in common to the CA channel and coupled to respective different ones of the first and second data channels, and each of which includes a coupling information pad. A first value may be inputted to the coupling information pad of one of the first and second semiconductor chips that is coupled to the first data channel, and a second value may be inputted to the coupling information pad of the other semiconductor chip that is coupled to the second data channel. Each of the first and second semiconductor chips selectively stores setting information using CA information applied to the CA channel and a value inputted to the corresponding coupling information pad.

公开(公告)号：US11625196B2

公开(公告)日：2023-04-11

申请号：US17406709

申请日：2021-08-19

申请人： SK hynix Inc.

发明人： Young-Jun Yoon ,  Hyun-Seung Kim

IPC分类号： G06F3/06

摘要： A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

公开(公告)号：US10102890B2

公开(公告)日：2018-10-16

申请号：US15701020

申请日：2017-09-11

申请人： SK hynix Inc.

发明人： Hyun-Seung Kim ,  Kwang-Soon Kim ,  Seung-Wook Oh ,  Jin-Youp Cha

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  G11C7/14 ,  G11C7/20 ,  G11C29/02

摘要： A semiconductor system includes a controller operatively coupled to a semiconductor device, the controller being suitable in a training mode for receiving an external signal and a first data signal from an external device and for transmitting the received external signal and the first data signal to the semiconductor device; and the semiconductor device being suitable in the training mode for determining a level of a reference voltage in response to the first data signal, and for transmitting a second data signal to the controller by buffering the external signal based on the reference voltage without performing a termination operation during an output period of the second data signal, wherein the controller controls an enable timing of the external signal by receiving the second data signal.

公开(公告)号：US09792969B1

公开(公告)日：2017-10-17

申请号：US15432214

申请日：2017-02-14

申请人： SK hynix Inc.

发明人： Hyun-Seung Kim ,  Kwang-Soon Kim ,  Seung-Wook Oh ,  Jin-Youp Cha

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/14 ,  G11C7/12 ,  G11C7/20

CPC分类号： G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C7/20 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： A semiconductor system includes a controller operatively coupled to a semiconductor device, the controller being suitable in a training mode for receiving an external signal and a first data signal from an external device and for transmitting the received external signal and the first data signal to the semiconductor device; and the semiconductor device being suitable in the training mode for determining a level of a reference voltage in response to the first data signal, and for transmitting a second data signal to the controller by buffering the external signal based on the reference voltage without performing a termination operation during an output period of the second data signal, wherein the controller controls an enable timing of the external signal by receiving the second data signal.